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authorKyösti Mälkki <kyosti.malkki@gmail.com>2014-04-17 15:07:32 +0300
committerKyösti Mälkki <kyosti.malkki@gmail.com>2014-04-20 20:03:46 +0200
commit35546deba642d3bb341d329fc1b9711727a5c50e (patch)
tree2eea5553868f26832e020b2375752757dc848865 /src/southbridge
parent981639233766a95b9642f7268519eafeccc57464 (diff)
downloadcoreboot-35546deba642d3bb341d329fc1b9711727a5c50e.tar.xz
AMD AGESA cimx/sb800: Drop APIC_ID_OFFSET and MAX_PHYSICAL_CPUS
All boards had APIC_ID_OFFSET=0 and MAX_PHYSICAL_CPUS=1. Change-Id: I6f08ea6de92a2af79fb3a99c5edd942b3a321c43 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5538 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Diffstat (limited to 'src/southbridge')
-rw-r--r--src/southbridge/amd/cimx/sb800/late.c5
1 files changed, 5 insertions, 0 deletions
diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c
index 3a534cdb48..219118aa25 100644
--- a/src/southbridge/amd/cimx/sb800/late.c
+++ b/src/southbridge/amd/cimx/sb800/late.c
@@ -370,6 +370,10 @@ static void sb800_enable(device_t dev)
case (0x14 << 3) | 0: /* 0:14:0 SMBUS */
printk(BIOS_INFO, "sm_init().\n");
clear_ioapic(IO_APIC_ADDR);
+#if CONFIG_CPU_AMD_AGESA
+ /* Assign the ioapic ID the next available number after the processor core local APIC IDs */
+ setup_ioapic(IO_APIC_ADDR, CONFIG_MAX_CPUS);
+#else
/* I/O APIC IDs are normally limited to 4-bits. Enforce this limit. */
#if (CONFIG_APIC_ID_OFFSET == 0 && CONFIG_MAX_CPUS * CONFIG_MAX_PHYSICAL_CPUS < 16)
/* Assign the ioapic ID the next available number after the processor core local APIC IDs */
@@ -380,6 +384,7 @@ static void sb800_enable(device_t dev)
#else
#error "The processor APIC IDs must be lifted to make room for the I/O APIC ID"
#endif
+#endif
break;
case (0x14 << 3) | 1: /* 0:14:1 IDE */