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| author | Arthur Heymans <arthur@aheymans.xyz> | 2019-10-21 20:02:14 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-10-22 20:07:11 +0000 |
| commit | 39bde7cacf104a27a547aaf1c599962f31447ff6 (patch) | |
| tree | 43f9b6834253978d72f99235aafd7ad8a910e50e /src/southbridge | |
| parent | ebcb0c5b882878b007e50ac7d44ec57aef5b16a2 (diff) | |
| download | coreboot-39bde7cacf104a27a547aaf1c599962f31447ff6.tar.xz | |
sb/intel/i82801gx: Set FERR# Mux Enable only on mobile platforms
This follows the ICH7 datasheets.
Change-Id: Ic8f6db8556662b03efead8c1b9e3074ffe24cd8b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36201
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge')
| -rw-r--r-- | src/southbridge/intel/i82801gx/early_cir.c | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/src/southbridge/intel/i82801gx/early_cir.c b/src/southbridge/intel/i82801gx/early_cir.c index 4f08a43b91..7543a777d5 100644 --- a/src/southbridge/intel/i82801gx/early_cir.c +++ b/src/southbridge/intel/i82801gx/early_cir.c @@ -29,9 +29,6 @@ void ich7_setup_cir(void) RCBA32(0x0214) = 0x10030549; RCBA32(0x0218) = 0x00020504; RCBA8(0x0220) = 0xc5; - reg32 = RCBA32(GCS); - reg32 |= (1 << 6); - RCBA32(GCS) = reg32; RCBA32_AND_OR(0x3430, ~(3 << 0), 1 << 0); RCBA16(0x0200) = 0x2008; RCBA8(0x2027) = 0x0d; @@ -51,5 +48,9 @@ void ich7_setup_cir(void) reg32 |= (5 << 16); RCBA32(0x2034) = reg32; } + /* FERR# MUX Enable (FME) */ + reg32 = RCBA32(GCS); + reg32 |= (1 << 6); + RCBA32(GCS) = reg32; } } |