summaryrefslogtreecommitdiff
path: root/src/southbridge
diff options
context:
space:
mode:
authorUwe Hermann <uwe@hermann-uwe.de>2010-12-18 13:22:37 +0000
committerUwe Hermann <uwe@hermann-uwe.de>2010-12-18 13:22:37 +0000
commit405721d45c8f7cd58c2466e43df8c2aee6f8e714 (patch)
treed9c981c99cf28f931032dabb26094494622f7bb6 /src/southbridge
parenta0360af0f1645d91b139022353f7a3a9f7f85f8a (diff)
downloadcoreboot-405721d45c8f7cd58c2466e43df8c2aee6f8e714.tar.xz
Fix a few whitespace and coding style issues.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6200 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge')
-rw-r--r--src/southbridge/intel/sch/audio.c63
-rw-r--r--src/southbridge/intel/sch/early_smbus.c1
-rw-r--r--src/southbridge/intel/sch/ide.c49
-rw-r--r--src/southbridge/intel/sch/lpc.c64
-rw-r--r--src/southbridge/intel/sch/mmc.c10
-rw-r--r--src/southbridge/intel/sch/pcie.c7
-rw-r--r--src/southbridge/intel/sch/reset.c7
-rw-r--r--src/southbridge/intel/sch/smbus.c4
-rw-r--r--src/southbridge/intel/sch/smbus.h7
-rw-r--r--src/southbridge/intel/sch/smi.c11
-rw-r--r--src/southbridge/intel/sch/south.c1
-rw-r--r--src/southbridge/intel/sch/usb.c12
-rw-r--r--src/southbridge/intel/sch/usb_client.c6
-rw-r--r--src/southbridge/intel/sch/usb_ehci.c6
14 files changed, 112 insertions, 136 deletions
diff --git a/src/southbridge/intel/sch/audio.c b/src/southbridge/intel/sch/audio.c
index 374e56c32e..7e4e22e9e7 100644
--- a/src/southbridge/intel/sch/audio.c
+++ b/src/southbridge/intel/sch/audio.c
@@ -96,7 +96,7 @@ static int codec_detect(u32 base)
if (set_bits(base + 0x08, 1, 1) == -1)
goto no_codec;
- /* Read in Codec location (BAR + 0xe)[2..0]*/
+ /* Read in Codec location (BAR + 0xe)[2..0] */
reg32 = read32(base + 0xe);
reg32 &= 0x0f;
if (!reg32)
@@ -112,7 +112,7 @@ no_codec:
return 0;
}
-const u32 * cim_verb_data = NULL;
+const u32 *cim_verb_data = NULL;
u32 cim_verb_data_size = 0;
static u32 find_verb(struct device *dev, u32 viddid, const u32 ** verb)
@@ -120,16 +120,16 @@ static u32 find_verb(struct device *dev, u32 viddid, const u32 ** verb)
printk(BIOS_DEBUG, "sch_audio: dev=%s\n", dev_path(dev));
printk(BIOS_DEBUG, "sch_audio: Reading viddid=%x\n", viddid);
- int idx=0;
+ int idx = 0;
while (idx < (cim_verb_data_size / sizeof(u32))) {
- u32 verb_size = 4 * cim_verb_data[idx+2]; // in u32
- verb_size++; // we ship an additional gain value
+ u32 verb_size = 4 * cim_verb_data[idx + 2]; // in u32
+ verb_size++; // we ship an additional gain value
if (cim_verb_data[idx] != viddid) {
- idx += verb_size + 3; // skip verb + header
+ idx += verb_size + 3; // skip verb + header
continue;
}
- *verb = &cim_verb_data[idx+3];
+ *verb = &cim_verb_data[idx + 3];
return verb_size;
}
@@ -149,8 +149,8 @@ static int wait_for_ready(u32 base)
int timeout = 50;
- while(timeout--) {
- u32 reg32 = read32(base + HDA_ICII_REG);
+ while (timeout--) {
+ u32 reg32 = read32(base + HDA_ICII_REG);
if (!(reg32 & HDA_ICII_BUSY))
return 0;
udelay(1);
@@ -173,23 +173,19 @@ static int wait_for_valid(u32 base)
int timeout = 25;
write32(base + 0x68, 1);
- while(timeout--)
- {
+ while (timeout--) {
udelay(1);
}
timeout = 50;
- while(timeout--)
- {
- u32 reg32 = read32(base + 0x68);
- if ((reg32 & ((1 << 1) | (1 << 0))) ==(1 << 1))
- {
+ while (timeout--) {
+ u32 reg32 = read32(base + 0x68);
+ if ((reg32 & ((1 << 1) | (1 << 0))) == (1 << 1)) {
write32(base + 0x68, 2);
- return 0;
+ return 0;
}
- udelay(1);
- }
-
+ udelay(1);
+ }
return 1;
}
@@ -213,7 +209,6 @@ static void codec_init(struct device *dev, u32 base, int addr)
if (wait_for_valid(base) == -1)
return;
-
reg32 = read32(base + 0x0);
printk(BIOS_DEBUG, "sch_audio: GCAP: %08x\n", reg32);
@@ -250,6 +245,7 @@ static void codec_init(struct device *dev, u32 base, int addr)
static void codecs_init(struct device *dev, u32 base, u32 codec_mask)
{
int i;
+
for (i = 2; i >= 0; i--) {
if (codec_mask & (1 << i))
codec_init(dev, base, i);
@@ -263,8 +259,6 @@ static void sch_audio_init(struct device *dev)
u32 codec_mask;
u32 reg32;
-
-
res = find_resource(dev, 0x10);
if (!res)
return;
@@ -274,17 +268,16 @@ static void sch_audio_init(struct device *dev)
// NOTE this will break as soon as the sch_audio get's a bar above
// 4G. Is there anything we can do about it?
- base = (u32)res->base;
- printk(BIOS_DEBUG, "sch_audio: base = %08x\n", (u32)base);
+ base = (u32) res->base;
+ printk(BIOS_DEBUG, "sch_audio: base = %08x\n", (u32) base);
codec_mask = codec_detect(base);
if (codec_mask) {
- printk(BIOS_DEBUG, "sch_audio: codec_mask = %02x\n", codec_mask);
+ printk(BIOS_DEBUG, "sch_audio: codec_mask = %02x\n",
+ codec_mask);
codecs_init(dev, base, codec_mask);
- }
- else
- {
- /* No audio codecs found disable HD audio controller*/
+ } else {
+ /* No audio codecs found disable HD audio controller */
pci_write_config32(dev, 0x10, 0);
pci_write_config32(dev, PCI_COMMAND, 0);
reg32 = pci_read_config32(dev, 0xFC);
@@ -292,19 +285,20 @@ static void sch_audio_init(struct device *dev)
}
}
-static void sch_audio_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+static void sch_audio_set_subsystem(device_t dev, unsigned vendor,
+ unsigned device)
{
if (!vendor || !device) {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
- pci_read_config32(dev, PCI_VENDOR_ID));
+ pci_read_config32(dev, PCI_VENDOR_ID));
} else {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
- ((device & 0xffff) << 16) | (vendor & 0xffff));
+ ((device & 0xffff) << 16) | (vendor & 0xffff));
}
}
static struct pci_operations sch_audio_pci_ops = {
- .set_subsystem = sch_audio_set_subsystem,
+ .set_subsystem = sch_audio_set_subsystem,
};
static struct device_operations sch_audio_ops = {
@@ -322,4 +316,3 @@ static const struct pci_driver sch_audio __pci_driver = {
.vendor = PCI_VENDOR_ID_INTEL,
.device = 0x811B,
};
-
diff --git a/src/southbridge/intel/sch/early_smbus.c b/src/southbridge/intel/sch/early_smbus.c
index 1fa88730bc..9b5353908f 100644
--- a/src/southbridge/intel/sch/early_smbus.c
+++ b/src/southbridge/intel/sch/early_smbus.c
@@ -60,4 +60,3 @@ int smbus_read_byte(unsigned device, unsigned address)
{
return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
}
-
diff --git a/src/southbridge/intel/sch/ide.c b/src/southbridge/intel/sch/ide.c
index 0ca98e08e2..471f17c692 100644
--- a/src/southbridge/intel/sch/ide.c
+++ b/src/southbridge/intel/sch/ide.c
@@ -5,8 +5,7 @@
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
+ * published by the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
@@ -24,45 +23,39 @@
#include <device/pci_ids.h>
/* PCI Configuration Space (D31:F1): IDE */
-#define INTR_LN 0x3c
-#define IDE_TIM_PRI 0x80 /* IDE timings, primary */
+#define INTR_LN 0x3c
+#define IDE_TIM_PRI 0x80 /* IDE timings, primary */
+
+extern int sch_port_access_read(int port, int reg, int bytes);
-extern int sch_port_access_read(int port,int reg, int bytes);
static void ide_init(struct device *dev)
{
- u32 ideTimingConfig;
- u32 reg32;
+ u32 ideTimingConfig, reg32;
+
printk(BIOS_DEBUG, "sch_ide: initializing... ");
reg32 = pci_read_config32(dev, PCI_COMMAND);
- pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_IO | PCI_COMMAND_MASTER);
-
- /* Program the clock */
+ pci_write_config32(dev, PCI_COMMAND,
+ reg32 | PCI_COMMAND_IO | PCI_COMMAND_MASTER);
- if (sch_port_access_read(5,3,4) & (1<<3))
- {
- /*533MHz
- Read PCI MC register*/
+ /* Program the clock. */
+ if (sch_port_access_read(5, 3, 4) & (1 << 3)) {
+ /* 533MHz, Read PCI MC register */
reg32 = pci_read_config32(dev, 0x60);
- pci_write_config32(dev,0x60,reg32 | 1);
- }
- else
- {
- /*400MHz*/
+ pci_write_config32(dev, 0x60, reg32 | 1);
+ } else {
+ /* 400MHz */
reg32 = pci_read_config32(dev, 0x60);
- reg32 &=~(1);
- pci_write_config32(dev,0x60,reg32);
+ reg32 &= ~1;
+ pci_write_config32(dev, 0x60, reg32);
}
-
- /* Enable primary IDE interface.
- 80=04 81=00 82=02 83=80
- */
+ /* Enable primary IDE interface. 80=04 81=00 82=02 83=80 */
ideTimingConfig = 0x80020000;
printk(BIOS_DEBUG, "IDE0 ");
pci_write_config32(dev, IDE_TIM_PRI, ideTimingConfig);
- /* Set Interrupt Line */
+ /* Set Interrupt Line. */
/* Interrupt Pin is set by D31IP.PIP */
printk(BIOS_DEBUG, "\n");
}
@@ -71,7 +64,7 @@ static void ide_set_subsystem(device_t dev, unsigned vendor, unsigned device)
{
if (!vendor || !device) {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
- pci_read_config32(dev, PCI_VENDOR_ID));
+ pci_read_config32(dev, PCI_VENDOR_ID));
} else {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
((device & 0xffff) << 16) | (vendor & 0xffff));
@@ -79,7 +72,7 @@ static void ide_set_subsystem(device_t dev, unsigned vendor, unsigned device)
}
static struct pci_operations ide_pci_ops = {
- .set_subsystem = ide_set_subsystem,
+ .set_subsystem = ide_set_subsystem,
};
static struct device_operations ide_ops = {
diff --git a/src/southbridge/intel/sch/lpc.c b/src/southbridge/intel/sch/lpc.c
index a9750189f7..ab180bb713 100644
--- a/src/southbridge/intel/sch/lpc.c
+++ b/src/southbridge/intel/sch/lpc.c
@@ -6,8 +6,7 @@
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
+ * published by the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
@@ -24,21 +23,19 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include <arch/io.h>
-
#include "chip.h"
-
-/*SCH LPC defines*/
-#define SCH_ACPI_CTL 0x58
-#define SCH_SIRQ_CTL 0x68
-#define PIRQA_ROUT 0x60
-#define PIRQB_ROUT 0x61
-#define PIRQC_ROUT 0x62
-#define PIRQD_ROUT 0x63
-#define PIRQE_ROUT 0x64
-#define PIRQF_ROUT 0x65
-#define PIRQG_ROUT 0x66
-#define PIRQH_ROUT 0x67
+/* SCH LPC defines */
+#define SCH_ACPI_CTL 0x58
+#define SCH_SIRQ_CTL 0x68
+#define PIRQA_ROUT 0x60
+#define PIRQB_ROUT 0x61
+#define PIRQC_ROUT 0x62
+#define PIRQD_ROUT 0x63
+#define PIRQE_ROUT 0x64
+#define PIRQF_ROUT 0x65
+#define PIRQG_ROUT 0x66
+#define PIRQH_ROUT 0x67
typedef struct southbridge_intel_sch_config config_t;
@@ -71,9 +68,11 @@ typedef struct southbridge_intel_sch_config config_t;
#define PIRQF 0x0A
#define PIRQG 0x0B
#define PIRQH 0x0C
+
static void sch_pirq_init(device_t dev)
{
device_t irq_dev;
+
/* Get the chip configuration */
config_t *config = dev->chip_info;
@@ -91,21 +90,27 @@ static void sch_pirq_init(device_t dev)
* I am not so sure anymore he was right.
*/
- for(irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next)
- {
- u8 int_pin=0, int_line=0;
+ for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {
+ u8 int_pin = 0, int_line = 0;
if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI)
continue;
int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN);
- switch (int_pin)
- {
- case 1: /* INTA# */ int_line = config->pirqa_routing; break;
- case 2: /* INTB# */ int_line = config->pirqb_routing; break;
- case 3: /* INTC# */ int_line = config->pirqc_routing; break;
- case 4: /* INTD# */ int_line = config->pirqd_routing; break;
+ switch (int_pin) {
+ case 1: /* INTA# */
+ int_line = config->pirqa_routing;
+ break;
+ case 2: /* INTB# */
+ int_line = config->pirqb_routing;
+ break;
+ case 3: /* INTC# */
+ int_line = config->pirqc_routing;
+ break;
+ case 4: /* INTD# */
+ int_line = config->pirqd_routing;
+ break;
}
if (!int_line)
@@ -114,13 +119,16 @@ static void sch_pirq_init(device_t dev)
pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, int_line);
}
}
+
static void sch_fixups(struct device *dev)
{
- u32 rcba_base;
- /* This needs to happen after PCI enumeration
- RCBA32(0x1d40) |= 1;*/
+ u32 rcba_base;
+
+ /* This needs to happen after PCI enumeration. */
+ /* RCBA32(0x1d40) |= 1; */
rcba_base = pci_read_config32(dev, 0xF0);
- /*Remove the enable bit*/
+
+ /* Remove the enable bit. */
rcba_base = rcba_base >> 1;
rcba_base = rcba_base << 1;
*((volatile u32 *)(rcba_base +0x104)) &= 0xFF00FFFF;
diff --git a/src/southbridge/intel/sch/mmc.c b/src/southbridge/intel/sch/mmc.c
index 9d69f0f3e0..cb8253bfc2 100644
--- a/src/southbridge/intel/sch/mmc.c
+++ b/src/southbridge/intel/sch/mmc.c
@@ -5,8 +5,7 @@
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
+ * published by the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
@@ -36,7 +35,8 @@ static void sch_mmc_init(struct device *dev)
printk(BIOS_DEBUG, "done.\n");
}
-static void sch_mmc_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+static void sch_mmc_set_subsystem(device_t dev, unsigned vendor,
+ unsigned device)
{
if (!vendor || !device) {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
@@ -45,11 +45,10 @@ static void sch_mmc_set_subsystem(device_t dev, unsigned vendor, unsigned device
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
((device & 0xffff) << 16) | (vendor & 0xffff));
}
-
}
static struct pci_operations lops_pci = {
- .set_subsystem = &sch_mmc_set_subsystem,
+ .set_subsystem = &sch_mmc_set_subsystem,
};
static struct device_operations sch_mmc_ops = {
@@ -79,4 +78,3 @@ static const struct pci_driver sch_mmc3 __pci_driver = {
.device = 0x811E,
};
-
diff --git a/src/southbridge/intel/sch/pcie.c b/src/southbridge/intel/sch/pcie.c
index a0ed7f9e5a..d818a18c81 100644
--- a/src/southbridge/intel/sch/pcie.c
+++ b/src/southbridge/intel/sch/pcie.c
@@ -46,7 +46,7 @@ static void pci_init(struct device *dev)
// reg16 &= ~(1 << 1); /* disable SERR */
//reg16 |= (1 << 2); /* ISA enable */
//pci_write_config16(dev, 0x3e, reg16);
- /*Slot implimented*/
+ /* Slot implemented. */
reg16 = pci_read_config16(dev, 0x42);
reg16 |= (1 << 8);
pci_write_config16(dev, 0x42, reg16);
@@ -54,15 +54,13 @@ static void pci_init(struct device *dev)
reg16 = pci_read_config16(dev, 0x48);
reg16 |= 0xf;
pci_write_config16(dev, 0x48, reg16);
-
}
static void pcie_set_subsystem(device_t dev, unsigned vendor, unsigned device)
{
/* NOTE: This is not the default position! */
if (!vendor || !device) {
- pci_write_config32(dev, 0x94,
- pci_read_config32(dev, 0));
+ pci_write_config32(dev, 0x94, pci_read_config32(dev, 0));
} else {
pci_write_config32(dev, 0x94,
((device & 0xffff) << 16) | (vendor & 0xffff));
@@ -95,4 +93,3 @@ static const struct pci_driver sch_pcie_port2 __pci_driver = {
.vendor = PCI_VENDOR_ID_INTEL,
.device = 0x8112,
};
-
diff --git a/src/southbridge/intel/sch/reset.c b/src/southbridge/intel/sch/reset.c
index af3dada2f7..17ab0a0661 100644
--- a/src/southbridge/intel/sch/reset.c
+++ b/src/southbridge/intel/sch/reset.c
@@ -23,12 +23,11 @@
void soft_reset(void)
{
- outb(0x04, 0xcf9);
+ outb(0x04, 0xcf9);
}
void hard_reset(void)
{
- outb(0x02, 0xcf9);
- outb(0x06, 0xcf9);
+ outb(0x02, 0xcf9);
+ outb(0x06, 0xcf9);
}
-
diff --git a/src/southbridge/intel/sch/smbus.c b/src/southbridge/intel/sch/smbus.c
index 2b32e506b0..79cd50f3f7 100644
--- a/src/southbridge/intel/sch/smbus.c
+++ b/src/southbridge/intel/sch/smbus.c
@@ -5,8 +5,7 @@
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
+ * published by the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
@@ -71,6 +70,7 @@ static struct device_operations smbus_ops = {
.ops_pci = &smbus_pci_ops,
};
+// FIXME
/* 82801GB/GR/GDH/GBM/GHM/GU (ICH7/ICH7R/ICH7DH/ICH7-M/ICH7-M DH/ICH7-U) */
static const struct pci_driver i82801gx_smbus __pci_driver = {
.ops = &smbus_ops,
diff --git a/src/southbridge/intel/sch/smbus.h b/src/southbridge/intel/sch/smbus.h
index c27eadb651..9b07a8c24e 100644
--- a/src/southbridge/intel/sch/smbus.h
+++ b/src/southbridge/intel/sch/smbus.h
@@ -51,7 +51,8 @@ static int smbus_wait_until_done(u16 smbus_base)
return loops ? 0 : -1;
}
-static int do_smbus_read_byte(unsigned smbus_base, unsigned device, unsigned address)
+static int do_smbus_read_byte(unsigned smbus_base, unsigned device,
+ unsigned address)
{
unsigned char global_status_register;
unsigned char byte;
@@ -76,8 +77,7 @@ static int do_smbus_read_byte(unsigned smbus_base, unsigned device, unsigned add
outb(0, smbus_base + SMBHSTDAT0);
/* Start the command */
- outb((inb(smbus_base + SMBHSTCTL) | 0x40),
- smbus_base + SMBHSTCTL);
+ outb((inb(smbus_base + SMBHSTCTL) | 0x40), smbus_base + SMBHSTCTL);
/* Poll for transaction completion */
if (smbus_wait_until_done(smbus_base) < 0) {
@@ -96,4 +96,3 @@ static int do_smbus_read_byte(unsigned smbus_base, unsigned device, unsigned add
}
return byte;
}
-
diff --git a/src/southbridge/intel/sch/smi.c b/src/southbridge/intel/sch/smi.c
index 07a7df47a5..046a1dd3c7 100644
--- a/src/southbridge/intel/sch/smi.c
+++ b/src/southbridge/intel/sch/smi.c
@@ -5,8 +5,7 @@
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
+ * published by the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
@@ -15,11 +14,9 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-
#include <device/device.h>
#include <device/pci.h>
#include <console/console.h>
@@ -152,7 +149,6 @@ static void dump_smi_status(u32 smi_sts)
printk(BIOS_DEBUG, "\n");
}
-
/**
* @brief read and clear GPE0_STS
* @return GPE0_STS register
@@ -210,7 +206,6 @@ static u32 reset_tco_status(void)
return reg32;
}
-
static void dump_tco_status(u32 tco_sts)
{
printk(BIOS_DEBUG, "TCO_STS: ");
@@ -230,8 +225,6 @@ static void dump_tco_status(u32 tco_sts)
printk(BIOS_DEBUG, "\n");
}
-
-
/**
* @brief Set the EOS bit
*/
diff --git a/src/southbridge/intel/sch/south.c b/src/southbridge/intel/sch/south.c
index e7c283f9a8..a98982dce7 100644
--- a/src/southbridge/intel/sch/south.c
+++ b/src/southbridge/intel/sch/south.c
@@ -24,4 +24,3 @@
struct chip_operations southbridge_intel_sch_ops = {
CHIP_NAME("Intel SCH Southbridge")
};
-
diff --git a/src/southbridge/intel/sch/usb.c b/src/southbridge/intel/sch/usb.c
index 95fc79be93..03aaba5967 100644
--- a/src/southbridge/intel/sch/usb.c
+++ b/src/southbridge/intel/sch/usb.c
@@ -6,8 +6,7 @@
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
+ * published by the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
@@ -28,12 +27,12 @@ static void usb_init(struct device *dev)
{
u32 reg32;
- /* USB Specification says the device must be Bus Master */
+ /* USB Specification says the device must be Bus Master. */
printk(BIOS_DEBUG, "UHCI: Setting up controller.. ");
reg32 = pci_read_config32(dev, PCI_COMMAND);
pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER);
- /*Disable clock gating*/
+ /* Disable clock gating. */
reg32 = pci_read_config32(dev, 0xFC);
reg32 |= (1 << 2);
pci_write_config32(dev, 0xFC, reg32);
@@ -61,7 +60,7 @@ static void usb_set_subsystem(device_t dev, unsigned vendor, unsigned device)
}
static struct pci_operations usb_pci_ops = {
- .set_subsystem = usb_set_subsystem,
+ .set_subsystem = usb_set_subsystem,
};
static struct device_operations usb_ops = {
@@ -73,17 +72,18 @@ static struct device_operations usb_ops = {
.ops_pci = &usb_pci_ops,
};
-/* */
static const struct pci_driver sch_usb0 __pci_driver = {
.ops = &usb_ops,
.vendor = PCI_VENDOR_ID_INTEL,
.device = 0x8114,
};
+
static const struct pci_driver sch_usb1 __pci_driver = {
.ops = &usb_ops,
.vendor = PCI_VENDOR_ID_INTEL,
.device = 0x8115,
};
+
static const struct pci_driver sch_usb2 __pci_driver = {
.ops = &usb_ops,
.vendor = PCI_VENDOR_ID_INTEL,
diff --git a/src/southbridge/intel/sch/usb_client.c b/src/southbridge/intel/sch/usb_client.c
index ea20c12bc0..8748e825d1 100644
--- a/src/southbridge/intel/sch/usb_client.c
+++ b/src/southbridge/intel/sch/usb_client.c
@@ -5,8 +5,7 @@
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
+ * published by the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
@@ -48,7 +47,7 @@ static void usb_client_set_subsystem(device_t dev, unsigned vendor, unsigned dev
}
static struct pci_operations lops_pci = {
- .set_subsystem = &usb_client_set_subsystem,
+ .set_subsystem = &usb_client_set_subsystem,
};
static struct device_operations usb_client_ops = {
@@ -60,7 +59,6 @@ static struct device_operations usb_client_ops = {
.ops_pci = &lops_pci,
};
-/* */
static const struct pci_driver sch_usb_client __pci_driver = {
.ops = &usb_client_ops,
.vendor = PCI_VENDOR_ID_INTEL,
diff --git a/src/southbridge/intel/sch/usb_ehci.c b/src/southbridge/intel/sch/usb_ehci.c
index 561a214825..3dbaeda077 100644
--- a/src/southbridge/intel/sch/usb_ehci.c
+++ b/src/southbridge/intel/sch/usb_ehci.c
@@ -51,7 +51,8 @@ static void usb_ehci_init(struct device *dev)
printk(BIOS_DEBUG, "done.\n");
}
-static void usb_ehci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+static void usb_ehci_set_subsystem(device_t dev, unsigned vendor,
+ unsigned device)
{
u8 access_cntl;
@@ -73,7 +74,7 @@ static void usb_ehci_set_subsystem(device_t dev, unsigned vendor, unsigned devic
}
static struct pci_operations lops_pci = {
- .set_subsystem = &usb_ehci_set_subsystem,
+ .set_subsystem = &usb_ehci_set_subsystem,
};
static struct device_operations usb_ehci_ops = {
@@ -85,7 +86,6 @@ static struct device_operations usb_ehci_ops = {
.ops_pci = &lops_pci,
};
-/* */
static const struct pci_driver sch_usb_ehci __pci_driver = {
.ops = &usb_ehci_ops,
.vendor = PCI_VENDOR_ID_INTEL,