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authorJulius Werner <jwerner@chromium.org>2019-03-07 17:07:26 -0800
committerPatrick Georgi <pgeorgi@google.com>2019-03-25 11:03:49 +0000
commit5d1f9a009647c741e8587015b14f1e852e1c489e (patch)
treeb6e87bac2f8a578b7bee6b73111e04bd3750eeb8 /src/southbridge
parent2de19038beffa154eefe40755b607aa9f94d9f9f (diff)
downloadcoreboot-5d1f9a009647c741e8587015b14f1e852e1c489e.tar.xz
Fix up remaining boolean uses of CONFIG_XXX to CONFIG(XXX)
This patch cleans up remaining uses of raw boolean Kconfig values I could find by wrapping them with CONFIG(). The remaining naked config value warnings in the code should all be false positives now (although the process was semi-manual and involved some eyeballing so I may have missed a few). Change-Id: Ifa0573a535addc3354a74e944c0920befb0666be Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31813 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/southbridge')
-rw-r--r--src/southbridge/amd/cimx/sb800/cfg.c2
-rw-r--r--src/southbridge/amd/cimx/sb900/early.c2
-rw-r--r--src/southbridge/intel/bd82x6x/lpc.c2
-rw-r--r--src/southbridge/intel/ibexpeak/lpc.c2
-rw-r--r--src/southbridge/nvidia/ck804/ck804.h2
5 files changed, 5 insertions, 5 deletions
diff --git a/src/southbridge/amd/cimx/sb800/cfg.c b/src/southbridge/amd/cimx/sb800/cfg.c
index 4487df3787..b52918d303 100644
--- a/src/southbridge/amd/cimx/sb800/cfg.c
+++ b/src/southbridge/amd/cimx/sb800/cfg.c
@@ -101,7 +101,7 @@ void sb800_cimx_config(AMDSBCFG *sb_config)
#endif
/* LPC */
/* SuperIO hardware monitor register access */
- sb_config->SioHwmPortEnable = CONFIG_SB_SUPERIO_HWM;
+ sb_config->SioHwmPortEnable = CONFIG(SB_SUPERIO_HWM);
/*
* GPP. default configure only enable port0 with 4 lanes,
diff --git a/src/southbridge/amd/cimx/sb900/early.c b/src/southbridge/amd/cimx/sb900/early.c
index 1109290bc7..5ebe47e5fb 100644
--- a/src/southbridge/amd/cimx/sb900/early.c
+++ b/src/southbridge/amd/cimx/sb900/early.c
@@ -40,7 +40,7 @@ void sb_poweron_init(void)
outb(0xEA, 0xCD6);
data = inb(0xCD7);
data &= !BIT0;
- if (!CONFIG_PCIB_ENABLE) {
+ if (!CONFIG(PCIB_ENABLE)) {
data |= BIT0;
}
outb(data, 0xCD7);
diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c
index eda16da6f7..e9e49649f2 100644
--- a/src/southbridge/intel/bd82x6x/lpc.c
+++ b/src/southbridge/intel/bd82x6x/lpc.c
@@ -418,7 +418,7 @@ static void enable_clock_gating(struct device *dev)
static void pch_set_acpi_mode(void)
{
- if (!acpi_is_wakeup_s3() && CONFIG_HAVE_SMI_HANDLER) {
+ if (!acpi_is_wakeup_s3() && CONFIG(HAVE_SMI_HANDLER)) {
#if ENABLE_ACPI_MODE_IN_COREBOOT
printk(BIOS_DEBUG, "Enabling ACPI via APMC:\n");
outb(APM_CNT_ACPI_ENABLE, APM_CNT); // Enable ACPI mode
diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c
index fe1d84a2b7..f4464f3b4d 100644
--- a/src/southbridge/intel/ibexpeak/lpc.c
+++ b/src/southbridge/intel/ibexpeak/lpc.c
@@ -433,7 +433,7 @@ static void enable_clock_gating(struct device *dev)
static void pch_set_acpi_mode(void)
{
- if (!acpi_is_wakeup_s3() && CONFIG_HAVE_SMI_HANDLER) {
+ if (!acpi_is_wakeup_s3() && CONFIG(HAVE_SMI_HANDLER)) {
#if ENABLE_ACPI_MODE_IN_COREBOOT
printk(BIOS_DEBUG, "Enabling ACPI via APMC:\n");
outb(APM_CNT_ACPI_ENABLE, APM_CNT); // Enable ACPI mode
diff --git a/src/southbridge/nvidia/ck804/ck804.h b/src/southbridge/nvidia/ck804/ck804.h
index fc99d9a848..5505691d1c 100644
--- a/src/southbridge/nvidia/ck804/ck804.h
+++ b/src/southbridge/nvidia/ck804/ck804.h
@@ -24,7 +24,7 @@
#endif
#define CK804B_BUSN 0x80
-#define CK804B_DEVN_BASE (!CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY ? CK804_DEVN_BASE : 1)
+#define CK804B_DEVN_BASE (!CONFIG(SB_HT_CHAIN_UNITID_OFFSET_ONLY) ? CK804_DEVN_BASE : 1)
#ifdef __PRE_RAM__
void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn);