sb/intel: Use common RCBA MACROs

This commit follows up on commit 2e464cf3 with Change-Id
I61fb3b01ff15ba2da2ee938addfa630c282c9870.

Change-Id: Iaf06d347e2da5680816b17f49523ac1a687798ba
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/29236
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: David Guckian
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

10 files changed, 14 insertions, 56 deletions

diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h
index ff55c393d7..5dac57eaf0 100644
--- a/src/southbridge/intel/bd82x6x/pch.h
+++ b/src/southbridge/intel/bd82x6x/pch.h
@@ -255,9 +255,6 @@ early_usb_init (const struct southbridge_usb_port *portmap);
 
 #define PMBASE		0x40
 
-/* Root Complex Register Block */
-#define RCBA		0xf0
-
 #define VCH		0x0000	/* 32bit */
 #define VCAP1		0x0004	/* 32bit */
 #define VCAP2		0x0008	/* 32bit */
diff --git a/src/southbridge/intel/common/rcba.h b/src/southbridge/intel/common/rcba.h
index b6cba8ea5f..e7482f9bdb 100644
--- a/src/southbridge/intel/common/rcba.h
+++ b/src/southbridge/intel/common/rcba.h
@@ -18,12 +18,12 @@
 #define SOUTHBRIDGE_INTEL_DEFAULT_RCBA_H
 
 #ifndef __ACPI__
+
 #define DEFAULT_RCBA		((u8 *)0xfed1c000)
-#else
-#define DEFAULT_RCBA	        0xfed1c000
-#endif
 
-#ifndef __ACPI__
+/* Root Complex Register Block */
+#define RCBA 0xf0
+#define RCBA_ENABLE 0x01
 
 #define RCBA8(x) (*((volatile u8 *)(DEFAULT_RCBA + x)))
 #define RCBA16(x) (*((volatile u16 *)(DEFAULT_RCBA + x)))
@@ -36,6 +36,10 @@
 #define RCBA32_AND_OR(x, and, or) RCBA_AND_OR(32, x, and, or)
 #define RCBA32_OR(x, or) RCBA_AND_OR(32, x, ~0UL, or)
 
+#else
+
+#define DEFAULT_RCBA	        0xfed1c000
 
 #endif /* __ACPI__ */
+
 #endif /* SOUTHBRIDGE_INTEL_DEFAULT_RCBA_H */
diff --git a/src/southbridge/intel/fsp_rangeley/soc.h b/src/southbridge/intel/fsp_rangeley/soc.h
index 1af57b6917..29ed943d3d 100644
--- a/src/southbridge/intel/fsp_rangeley/soc.h
+++ b/src/southbridge/intel/fsp_rangeley/soc.h
@@ -41,11 +41,8 @@
 /* Southbridge internal device MEM BARs (Set to match FSP settings) */
 #define DEFAULT_IBASE		0xfed08000
 #define DEFAULT_PBASE		0xfed03000
-#ifndef __ACPI__
-#define DEFAULT_RCBA		((u8 *)0xfed1c000)
-#else
-#define DEFAULT_RCBA		0xfed1c000
-#endif
+
+#include <southbridge/intel/common/rcba.h>
 
 #ifndef __ACPI__
 #define DEBUG_PERIODIC_SMIS 0
@@ -171,21 +168,6 @@ void rangeley_sb_early_initialization(void);
 #define SMB_SMI_EN		(1 << 1)
 #define HST_EN			(1 << 0)
 
-/* Root Complex Register Block */
-#define RCBA		0xf0
-#define  RCBA_ENABLE 0x01
-
-#define RCBA8(x) *((volatile u8 *)(DEFAULT_RCBA + x))
-#define RCBA16(x) *((volatile u16 *)(DEFAULT_RCBA + x))
-#define RCBA32(x) *((volatile u32 *)(DEFAULT_RCBA + x))
-
-#define RCBA_AND_OR(bits, x, and, or) \
-        RCBA##bits(x) = ((RCBA##bits(x) & (and)) | (or))
-#define RCBA8_AND_OR(x, and, or)  RCBA_AND_OR(8, x, and, or)
-#define RCBA16_AND_OR(x, and, or) RCBA_AND_OR(16, x, and, or)
-#define RCBA32_AND_OR(x, and, or) RCBA_AND_OR(32, x, and, or)
-#define RCBA32_OR(x, or) RCBA_AND_OR(32, x, ~0UL, or)
-
 /* Root Port configuration space hide */
 #define RPFN_HIDE(port)         (1 << (((port) * 4) + 3))
 /* Get the function number assigned to a Root Port */
diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h
index 9fd9fd6273..395cdd13cf 100644
--- a/src/southbridge/intel/i82801gx/i82801gx.h
+++ b/src/southbridge/intel/i82801gx/i82801gx.h
@@ -184,9 +184,6 @@ int southbridge_detect_s3_resume(void);
 
 #define PMBASE		0x40
 
-/* Root Complex Register Block */
-#define RCBA		0xf0
-
 #define VCH		0x0000	/* 32bit */
 #define VCAP1		0x0004	/* 32bit */
 #define VCAP2		0x0008	/* 32bit */
diff --git a/src/southbridge/intel/i82801ix/early_init.c b/src/southbridge/intel/i82801ix/early_init.c
index c40f9b73ea..f7e2fd2621 100644
--- a/src/southbridge/intel/i82801ix/early_init.c
+++ b/src/southbridge/intel/i82801ix/early_init.c
@@ -22,7 +22,7 @@ void i82801ix_early_init(void)
 	const pci_devfn_t d31f0 = PCI_DEV(0, 0x1f, 0);
 
 	/* Set up RCBA. */
-	pci_write_config32(d31f0, D31F0_RCBA, (uintptr_t)DEFAULT_RCBA | 1);
+	pci_write_config32(d31f0, RCBA, (uintptr_t)DEFAULT_RCBA | 1);
 
 	/* Set up PMBASE. */
 	pci_write_config32(d31f0, D31F0_PMBASE, DEFAULT_PMBASE | 1);
diff --git a/src/southbridge/intel/i82801ix/i82801ix.h b/src/southbridge/intel/i82801ix/i82801ix.h
index f094ed8920..ddecc0cd71 100644
--- a/src/southbridge/intel/i82801ix/i82801ix.h
+++ b/src/southbridge/intel/i82801ix/i82801ix.h
@@ -111,7 +111,6 @@
 #define D31F0_CxSTATE_CNF	0xa9
 #define D31F0_C4TIMING_CNT	0xaa
 #define D31F0_GPIO_ROUT		0xb8
-#define D31F0_RCBA		0xf0
 
 /* GEN_PMCON_3 bits */
 #define RTC_BATTERY_DEAD	(1 << 2)
diff --git a/src/southbridge/intel/i82801jx/bootblock.c b/src/southbridge/intel/i82801jx/bootblock.c
index cc685c4544..911361af6b 100644
--- a/src/southbridge/intel/i82801jx/bootblock.c
+++ b/src/southbridge/intel/i82801jx/bootblock.c
@@ -34,6 +34,6 @@ static void bootblock_southbridge_init(void)
 	enable_spi_prefetch();
 
 	/* Enable RCBA */
-	pci_write_config32(PCI_DEV(0, 0x1f, 0), D31F0_RCBA,
+	pci_write_config32(PCI_DEV(0, 0x1f, 0), RCBA,
 			(uintptr_t)DEFAULT_RCBA | 1);
 }
diff --git a/src/southbridge/intel/i82801jx/i82801jx.h b/src/southbridge/intel/i82801jx/i82801jx.h
index 4813dd83b3..ad3b38177a 100644
--- a/src/southbridge/intel/i82801jx/i82801jx.h
+++ b/src/southbridge/intel/i82801jx/i82801jx.h
@@ -114,7 +114,6 @@
 #define D31F0_CxSTATE_CNF	0xa9
 #define D31F0_C4TIMING_CNT	0xaa
 #define D31F0_GPIO_ROUT		0xb8
-#define D31F0_RCBA		0xf0
 
 /* GEN_PMCON_3 bits */
 #define RTC_BATTERY_DEAD	(1 << 2)
diff --git a/src/southbridge/intel/ibexpeak/pch.h b/src/southbridge/intel/ibexpeak/pch.h
index 19add778f3..13579460dc 100644
--- a/src/southbridge/intel/ibexpeak/pch.h
+++ b/src/southbridge/intel/ibexpeak/pch.h
@@ -227,9 +227,6 @@ void southbridge_configure_default_intmap(void);
 
 #define PMBASE		0x40
 
-/* Root Complex Register Block */
-#define RCBA		0xf0
-
 #define VCH		0x0000	/* 32bit */
 #define VCAP1		0x0004	/* 32bit */
 #define VCAP2		0x0008	/* 32bit */
diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h
index 2aa6b48785..026fcdd383 100644
--- a/src/southbridge/intel/lynxpoint/pch.h
+++ b/src/southbridge/intel/lynxpoint/pch.h
@@ -83,11 +83,8 @@
 #endif
 
 #define HPET_ADDR		0xfed00000
-#ifndef __ACPI__
-#define DEFAULT_RCBA		((u8 *)0xfed1c000)
-#else
-#define DEFAULT_RCBA		0xfed1c000
-#endif
+
+#include <southbridge/intel/common/rcba.h>
 
 #ifndef __ACPI__
 
@@ -477,20 +474,6 @@ void mainboard_config_superio(void);
 
 #define PMBASE		0x40
 
-/* Root Complex Register Block */
-#define RCBA		0xf0
-
-#define RCBA8(x) *((volatile u8 *)(DEFAULT_RCBA + x))
-#define RCBA16(x) *((volatile u16 *)(DEFAULT_RCBA + x))
-#define RCBA32(x) *((volatile u32 *)(DEFAULT_RCBA + x))
-
-#define RCBA_AND_OR(bits, x, and, or) \
-        RCBA##bits(x) = ((RCBA##bits(x) & (and)) | (or))
-#define RCBA8_AND_OR(x, and, or)  RCBA_AND_OR(8, x, and, or)
-#define RCBA16_AND_OR(x, and, or) RCBA_AND_OR(16, x, and, or)
-#define RCBA32_AND_OR(x, and, or) RCBA_AND_OR(32, x, and, or)
-#define RCBA32_OR(x, or) RCBA_AND_OR(32, x, ~0UL, or)
-
 #define VCH		0x0000	/* 32bit */
 #define VCAP1		0x0004	/* 32bit */
 #define VCAP2		0x0008	/* 32bit */