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| author | Aaron Durbin <adurbin@chromium.org> | 2019-12-27 13:48:14 -0700 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2020-01-03 23:06:41 +0000 |
| commit | 8b1cdd55a9328dc58430fb6efcea8993d864437f (patch) | |
| tree | 5b49a5e1dc211f05629c9723fe3868e6b16714bc /src/southbridge | |
| parent | 173620a88dfe3afec1733d7bec8846406f9c8946 (diff) | |
| download | coreboot-8b1cdd55a9328dc58430fb6efcea8993d864437f.tar.xz | |
drivers/spi/sst: remove unnecessary byte programming
The SST25VF064C supports page programming mode like other spi flash
parts in that there isn't an offset requirement. Remove this
check and single byte program because CMD_SST_BP (0x2) is the
same as page programming command. Lastly, for clariy purposes provide
a CMD_SST_PP to explicitly indicate page programming despite the
values (0x2) being the same as byte programming for the other parts.
Change-Id: I84eea0b044ccac6c6f26ea4cb42f4c13cf8f5173
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37959
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge')
0 files changed, 0 insertions, 0 deletions