summaryrefslogtreecommitdiff
path: root/src/southbridge
diff options
context:
space:
mode:
authorVladimir Serbinenko <phcoder@gmail.com>2013-03-12 15:53:44 +0100
committerMarc Jones <marc.jones@se-eng.com>2013-04-16 15:34:09 +0200
commit8c937c7e3cb9768c83e49a445f13e87a58d79768 (patch)
tree66e8ae321b161ff07da717b4554e56e3c4c6c034 /src/southbridge
parent8a2bc62d4ce86689353021843b2377c8bb8fab56 (diff)
downloadcoreboot-8c937c7e3cb9768c83e49a445f13e87a58d79768.tar.xz
Intel Panther Point PCH: Use 2 << 24 to clarify that APIC ID is 2
Commit »Add support for Intel Panther Point PCH« (8e073829) [1] used `1 << 25` to set the APIC ID of 2. Using `2 << 24`, which is the same value, instead makes it clear, that the APIC ID is 2. [1] http://review.coreboot.org/853 Change-Id: I5044dc470120cde2d2cdfc6e9ead17ddb47b6453 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3100 Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Diffstat (limited to 'src/southbridge')
-rw-r--r--src/southbridge/intel/bd82x6x/lpc.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c
index df37ddc4f8..7bcadc94a9 100644
--- a/src/southbridge/intel/bd82x6x/lpc.c
+++ b/src/southbridge/intel/bd82x6x/lpc.c
@@ -52,7 +52,7 @@ static void pch_enable_apic(struct device *dev)
pci_write_config8(dev, ACPI_CNTL, 0x80);
*ioapic_index = 0;
- *ioapic_data = (1 << 25);
+ *ioapic_data = (2 << 24);
/* affirm full set of redirection table entries ("write once") */
*ioapic_index = 1;
@@ -63,7 +63,7 @@ static void pch_enable_apic(struct device *dev)
*ioapic_index = 0;
reg32 = *ioapic_data;
printk(BIOS_DEBUG, "Southbridge APIC ID = %x\n", (reg32 >> 24) & 0x0f);
- if (reg32 != (1 << 25))
+ if (reg32 != (2 << 24))
die("APIC Error\n");
printk(BIOS_SPEW, "Dumping IOAPIC registers\n");