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authorNico Huber <nico.h@gmx.de>2018-11-14 00:00:35 +0100
committerNico Huber <nico.h@gmx.de>2019-01-06 15:54:19 +0000
commit9faae2b939d0c83632baeefe80bef1739e125018 (patch)
treea3d62f5f14994f1facc2389d189796a836bd8e81 /src/southbridge
parentd2f678d3bd6ca4c05fa5c652d6cdf4623543e576 (diff)
downloadcoreboot-9faae2b939d0c83632baeefe80bef1739e125018.tar.xz
Kconfig: Unify power-after-failure options
The newest and most useful incarnation was hiding in soc/intel/common/. We move it into the Mainboard menu and extend it with various flags to be selected to control the default and which options are visible. Also add a new `int` config MAINBOARD_POWER_FAILURE_STATE that moves the boolean to int conversion into Kconfig: 0 - S5 1 - S0 2 - previous state This patch focuses on the Kconfig code. The C code could be unified as well, e.g. starting with a common enum and safe wrapper around the get_option() call. TEST=Did what-jenkins-does with and without this commit and compared binaries. Nothing changed for the default configurations. Change-Id: I61259f864c8a8cfc7099cc2699059f972fa056c0 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/29680 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/southbridge')
-rw-r--r--src/southbridge/amd/agesa/hudson/sm.c4
-rw-r--r--src/southbridge/amd/amd8111/Kconfig1
-rw-r--r--src/southbridge/amd/amd8111/acpi.c7
-rw-r--r--src/southbridge/amd/pi/hudson/sm.c4
-rw-r--r--src/southbridge/amd/sb700/Kconfig2
-rw-r--r--src/southbridge/amd/sb700/sm.c8
-rw-r--r--src/southbridge/amd/sb800/sm.c4
-rw-r--r--src/southbridge/intel/bd82x6x/lpc.c2
-rw-r--r--src/southbridge/intel/common/Kconfig2
-rw-r--r--src/southbridge/intel/common/pmutil.h4
-rw-r--r--src/southbridge/intel/common/smihandler.c2
-rw-r--r--src/southbridge/intel/fsp_rangeley/soc.h4
-rw-r--r--src/southbridge/intel/i82801dx/Kconfig2
-rw-r--r--src/southbridge/intel/i82801dx/i82801dx.h4
-rw-r--r--src/southbridge/intel/i82801dx/lpc.c2
-rw-r--r--src/southbridge/intel/i82801dx/smihandler.c2
-rw-r--r--src/southbridge/intel/i82801gx/i82801gx.h4
-rw-r--r--src/southbridge/intel/i82801gx/lpc.c2
-rw-r--r--src/southbridge/intel/i82801ix/i82801ix.h5
-rw-r--r--src/southbridge/intel/i82801ix/lpc.c2
-rw-r--r--src/southbridge/intel/i82801jx/Kconfig2
-rw-r--r--src/southbridge/intel/i82801jx/i82801jx.h5
-rw-r--r--src/southbridge/intel/i82801jx/lpc.c2
-rw-r--r--src/southbridge/intel/ibexpeak/Kconfig2
-rw-r--r--src/southbridge/intel/ibexpeak/lpc.c2
-rw-r--r--src/southbridge/intel/ibexpeak/pch.h4
-rw-r--r--src/southbridge/intel/ibexpeak/smihandler.c2
-rw-r--r--src/southbridge/intel/lynxpoint/Kconfig2
-rw-r--r--src/southbridge/intel/lynxpoint/lpc.c2
-rw-r--r--src/southbridge/intel/lynxpoint/pch.h4
-rw-r--r--src/southbridge/intel/lynxpoint/smihandler.c2
-rw-r--r--src/southbridge/nvidia/ck804/Kconfig1
-rw-r--r--src/southbridge/nvidia/ck804/lpc.c6
-rw-r--r--src/southbridge/nvidia/mcp55/Kconfig1
-rw-r--r--src/southbridge/nvidia/mcp55/lpc.c6
35 files changed, 31 insertions, 79 deletions
diff --git a/src/southbridge/amd/agesa/hudson/sm.c b/src/southbridge/amd/agesa/hudson/sm.c
index 927c73fb01..2cd1ff20dc 100644
--- a/src/southbridge/amd/agesa/hudson/sm.c
+++ b/src/southbridge/amd/agesa/hudson/sm.c
@@ -30,10 +30,6 @@
#define MAINBOARD_POWER_OFF 0
#define MAINBOARD_POWER_ON 1
-#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
-#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON
-#endif
-
#define BIT0 (1 << 0)
#define BIT1 (1 << 1)
#define BIT2 (1 << 2)
diff --git a/src/southbridge/amd/amd8111/Kconfig b/src/southbridge/amd/amd8111/Kconfig
index 1436d8cc83..a3abf89d9e 100644
--- a/src/southbridge/amd/amd8111/Kconfig
+++ b/src/southbridge/amd/amd8111/Kconfig
@@ -16,6 +16,7 @@
config SOUTHBRIDGE_AMD_AMD8111
bool
select IOAPIC
+ select HAVE_POWER_STATE_AFTER_FAILURE
config BOOTBLOCK_SOUTHBRIDGE_INIT
string
diff --git a/src/southbridge/amd/amd8111/acpi.c b/src/southbridge/amd/amd8111/acpi.c
index 8dc2007500..5216a105d6 100644
--- a/src/southbridge/amd/amd8111/acpi.c
+++ b/src/southbridge/amd/amd8111/acpi.c
@@ -29,11 +29,6 @@
#define SLOW_CPU_OFF 0
#define SLOW_CPU__ON 1
-#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
-#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON
-#endif
-
-
static int lsmbus_recv_byte(struct device *dev)
{
unsigned int device;
@@ -148,7 +143,7 @@ static void acpi_init(struct device *dev)
pci_write_config8(dev, 0x41, byte | (1<<6)|(1<<5));
/* power on after power fail */
- on = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
+ on = CONFIG_MAINBOARD_POWER_FAILURE_STATE;
get_option(&on, "power_on_after_fail");
byte = pci_read_config8(dev, PREVIOUS_POWER_STATE);
byte &= ~0x40;
diff --git a/src/southbridge/amd/pi/hudson/sm.c b/src/southbridge/amd/pi/hudson/sm.c
index 5aeae8e918..6d1c2bcbdb 100644
--- a/src/southbridge/amd/pi/hudson/sm.c
+++ b/src/southbridge/amd/pi/hudson/sm.c
@@ -30,10 +30,6 @@
#define MAINBOARD_POWER_OFF 0
#define MAINBOARD_POWER_ON 1
-#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
-#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON
-#endif
-
/*
* HUDSON enables all USB controllers by default in SMBUS Control.
* HUDSON enables SATA by default in SMBUS Control.
diff --git a/src/southbridge/amd/sb700/Kconfig b/src/southbridge/amd/sb700/Kconfig
index 6d62e67d37..58dc75a5de 100644
--- a/src/southbridge/amd/sb700/Kconfig
+++ b/src/southbridge/amd/sb700/Kconfig
@@ -23,6 +23,8 @@ config SOUTHBRIDGE_SPECIFIC_OPTIONS # dummy
select IOAPIC
select HAVE_USBDEBUG_OPTIONS
select SMBUS_HAS_AUX_CHANNELS
+ select HAVE_POWER_STATE_AFTER_FAILURE
+ select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE
config SOUTHBRIDGE_AMD_SB700_33MHZ_SPI
bool "Enable high speed SPI clock"
diff --git a/src/southbridge/amd/sb700/sm.c b/src/southbridge/amd/sb700/sm.c
index 64c6db3072..4c3992d8d5 100644
--- a/src/southbridge/amd/sb700/sm.c
+++ b/src/southbridge/amd/sb700/sm.c
@@ -44,10 +44,6 @@ enum power_mode {
POWER_MODE_LAST = 2,
};
-#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
-#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL POWER_MODE_ON
-#endif
-
static const char *power_mode_names[] = {
[POWER_MODE_OFF] = "off",
[POWER_MODE_ON] = "on",
@@ -152,11 +148,11 @@ static void sm_init(struct device *dev)
pm_iowrite(0x53, byte);
/* power after power fail */
- power_state = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
+ power_state = CONFIG_MAINBOARD_POWER_FAILURE_STATE;
get_option(&power_state, "power_on_after_fail");
if (power_state > 2) {
printk(BIOS_WARNING, "Invalid power_on_after_fail setting, using default\n");
- power_state = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
+ power_state = CONFIG_MAINBOARD_POWER_FAILURE_STATE;
}
byte = pm_ioread(0x74);
byte &= ~0x03;
diff --git a/src/southbridge/amd/sb800/sm.c b/src/southbridge/amd/sb800/sm.c
index fdb6283fb0..1d2daed81c 100644
--- a/src/southbridge/amd/sb800/sm.c
+++ b/src/southbridge/amd/sb800/sm.c
@@ -32,10 +32,6 @@
#define MAINBOARD_POWER_OFF 0
#define MAINBOARD_POWER_ON 1
-#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
-#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON
-#endif
-
#define BIT0 (1 << 0)
#define BIT1 (1 << 1)
#define BIT2 (1 << 2)
diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c
index d3da239321..e13c666024 100644
--- a/src/southbridge/intel/bd82x6x/lpc.c
+++ b/src/southbridge/intel/bd82x6x/lpc.c
@@ -181,7 +181,7 @@ static void pch_power_options(struct device *dev)
/* Get the chip configuration */
config_t *config = dev->chip_info;
- int pwr_on=CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
+ int pwr_on = CONFIG_MAINBOARD_POWER_FAILURE_STATE;
int nmi_option;
/* Which state do we want to goto after g3 (power restored)?
diff --git a/src/southbridge/intel/common/Kconfig b/src/southbridge/intel/common/Kconfig
index ba53f68423..6a96277844 100644
--- a/src/southbridge/intel/common/Kconfig
+++ b/src/southbridge/intel/common/Kconfig
@@ -29,6 +29,8 @@ config HAVE_INTEL_CHIPSET_LOCKDOWN
config SOUTHBRIDGE_INTEL_COMMON_SMM
def_bool n
+ select HAVE_POWER_STATE_AFTER_FAILURE
+ select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE
config SOUTHBRIDGE_INTEL_COMMON_ACPI_MADT
bool
diff --git a/src/southbridge/intel/common/pmutil.h b/src/southbridge/intel/common/pmutil.h
index 2076a3d2c1..7f07a724a3 100644
--- a/src/southbridge/intel/common/pmutil.h
+++ b/src/southbridge/intel/common/pmutil.h
@@ -45,10 +45,6 @@
#define MAINBOARD_POWER_ON 1
#define MAINBOARD_POWER_KEEP 2
-#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
-#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON
-#endif
-
#define PM1_STS 0x00
#define WAK_STS (1 << 15)
#define PCIEXPWAK_STS (1 << 14)
diff --git a/src/southbridge/intel/common/smihandler.c b/src/southbridge/intel/common/smihandler.c
index 6347ad663b..4525934970 100644
--- a/src/southbridge/intel/common/smihandler.c
+++ b/src/southbridge/intel/common/smihandler.c
@@ -112,7 +112,7 @@ static void southbridge_smi_sleep(void)
u8 reg8;
u32 reg32;
u8 slp_typ;
- u8 s5pwr = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
+ u8 s5pwr = CONFIG_MAINBOARD_POWER_FAILURE_STATE;
// save and recover RTC port values
u8 tmp70, tmp72;
diff --git a/src/southbridge/intel/fsp_rangeley/soc.h b/src/southbridge/intel/fsp_rangeley/soc.h
index 02e410d8e7..1af57b6917 100644
--- a/src/southbridge/intel/fsp_rangeley/soc.h
+++ b/src/southbridge/intel/fsp_rangeley/soc.h
@@ -80,10 +80,6 @@ void rangeley_sb_early_initialization(void);
#define MAINBOARD_POWER_ON 1
#define MAINBOARD_POWER_KEEP 2
-#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
-#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON
-#endif
-
#define SOC_EHCI1_DEV PCI_DEV(0, 0x1d, 0)
#define PCIE_DEV_SLOT0 1
#define PCIE_DEV_SLOT1 2
diff --git a/src/southbridge/intel/i82801dx/Kconfig b/src/southbridge/intel/i82801dx/Kconfig
index 827f6bb0f6..5670e162cf 100644
--- a/src/southbridge/intel/i82801dx/Kconfig
+++ b/src/southbridge/intel/i82801dx/Kconfig
@@ -22,6 +22,8 @@ config SOUTHBRIDGE_INTEL_I82801DX
select HAVE_USBDEBUG
select SOUTHBRIDGE_INTEL_COMMON
select SOUTHBRIDGE_INTEL_COMMON_SMBUS
+ select HAVE_POWER_STATE_AFTER_FAILURE
+ select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE
if SOUTHBRIDGE_INTEL_I82801DX
diff --git a/src/southbridge/intel/i82801dx/i82801dx.h b/src/southbridge/intel/i82801dx/i82801dx.h
index 8c7da55ff1..678d5d78b9 100644
--- a/src/southbridge/intel/i82801dx/i82801dx.h
+++ b/src/southbridge/intel/i82801dx/i82801dx.h
@@ -45,10 +45,6 @@ int smbus_read_byte(unsigned device, unsigned address);
#define MAINBOARD_POWER_ON 1
#define MAINBOARD_POWER_KEEP 2
-#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
-#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON
-#endif
-
/*
* 000 = Non-combined. P0 is primary master. P1 is secondary master.
* 001 = Non-combined. P0 is secondary master. P1 is primary master.
diff --git a/src/southbridge/intel/i82801dx/lpc.c b/src/southbridge/intel/i82801dx/lpc.c
index 925251da2a..3c74e98f59 100644
--- a/src/southbridge/intel/i82801dx/lpc.c
+++ b/src/southbridge/intel/i82801dx/lpc.c
@@ -103,7 +103,7 @@ static void i82801dx_power_options(struct device *dev)
u32 reg32;
const char *state;
- int pwr_on = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
+ int pwr_on = CONFIG_MAINBOARD_POWER_FAILURE_STATE;
int nmi_option;
/* Which state do we want to goto after g3 (power restored)?
diff --git a/src/southbridge/intel/i82801dx/smihandler.c b/src/southbridge/intel/i82801dx/smihandler.c
index b2b4662f60..e7a9589116 100644
--- a/src/southbridge/intel/i82801dx/smihandler.c
+++ b/src/southbridge/intel/i82801dx/smihandler.c
@@ -276,7 +276,7 @@ static void southbridge_smi_sleep(unsigned int node, smm_state_save_area_t *stat
* CMOS or even better from GNVS. Right now it's hard
* coded at compile time.
*/
- u8 s5pwr = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
+ u8 s5pwr = CONFIG_MAINBOARD_POWER_FAILURE_STATE;
/* First, disable further SMIs */
reg8 = inb(pmbase + SMI_EN);
diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h
index 40c2bb72e3..29c8736552 100644
--- a/src/southbridge/intel/i82801gx/i82801gx.h
+++ b/src/southbridge/intel/i82801gx/i82801gx.h
@@ -58,10 +58,6 @@ int southbridge_detect_s3_resume(void);
#define MAINBOARD_POWER_ON 1
#define MAINBOARD_POWER_KEEP 2
-#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
-#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON
-#endif
-
/* PCI Configuration Space (D30:F0): PCI2PCI */
#define PSTS 0x06
#define SMLT 0x1b
diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c
index c16b8a6649..e8cfc74ac1 100644
--- a/src/southbridge/intel/i82801gx/lpc.c
+++ b/src/southbridge/intel/i82801gx/lpc.c
@@ -172,7 +172,7 @@ static void i82801gx_power_options(struct device *dev)
/* Get the chip configuration */
config_t *config = dev->chip_info;
- int pwr_on = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
+ int pwr_on = CONFIG_MAINBOARD_POWER_FAILURE_STATE;
int nmi_option;
/* Which state do we want to goto after g3 (power restored)?
diff --git a/src/southbridge/intel/i82801ix/i82801ix.h b/src/southbridge/intel/i82801ix/i82801ix.h
index aed1999054..f094ed8920 100644
--- a/src/southbridge/intel/i82801ix/i82801ix.h
+++ b/src/southbridge/intel/i82801ix/i82801ix.h
@@ -85,11 +85,6 @@
#define MAINBOARD_POWER_ON 1
#define MAINBOARD_POWER_KEEP 2
-#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
-#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON
-#endif
-
-
/* D31:F0 LPC bridge */
#define D31F0_PMBASE 0x40
#define D31F0_ACPI_CNTL 0x44
diff --git a/src/southbridge/intel/i82801ix/lpc.c b/src/southbridge/intel/i82801ix/lpc.c
index b809a4e3b7..dd37a0bd74 100644
--- a/src/southbridge/intel/i82801ix/lpc.c
+++ b/src/southbridge/intel/i82801ix/lpc.c
@@ -170,7 +170,7 @@ static void i82801ix_power_options(struct device *dev)
/* Get the chip configuration */
config_t *config = dev->chip_info;
- int pwr_on=CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
+ int pwr_on = CONFIG_MAINBOARD_POWER_FAILURE_STATE;
int nmi_option;
/* BIOS must program... */
diff --git a/src/southbridge/intel/i82801jx/Kconfig b/src/southbridge/intel/i82801jx/Kconfig
index b215812601..2bc18fa8fe 100644
--- a/src/southbridge/intel/i82801jx/Kconfig
+++ b/src/southbridge/intel/i82801jx/Kconfig
@@ -30,6 +30,8 @@ config SOUTHBRIDGE_INTEL_I82801JX
select COMMON_FADT
select SOUTHBRIDGE_INTEL_COMMON_SMM
select ACPI_INTEL_HARDWARE_SLEEP_VALUES
+ select HAVE_POWER_STATE_AFTER_FAILURE
+ select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE
if SOUTHBRIDGE_INTEL_I82801JX
diff --git a/src/southbridge/intel/i82801jx/i82801jx.h b/src/southbridge/intel/i82801jx/i82801jx.h
index 3c09746f81..4813dd83b3 100644
--- a/src/southbridge/intel/i82801jx/i82801jx.h
+++ b/src/southbridge/intel/i82801jx/i82801jx.h
@@ -76,11 +76,6 @@
#define MAINBOARD_POWER_ON 1
#define MAINBOARD_POWER_KEEP 2
-#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
-#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON
-#endif
-
-
/* D31:F0 LPC bridge */
#define D31F0_PMBASE 0x40
#define PMBASE D31F0_PMBASE
diff --git a/src/southbridge/intel/i82801jx/lpc.c b/src/southbridge/intel/i82801jx/lpc.c
index 2ff2acd095..0f82f90455 100644
--- a/src/southbridge/intel/i82801jx/lpc.c
+++ b/src/southbridge/intel/i82801jx/lpc.c
@@ -172,7 +172,7 @@ static void i82801jx_power_options(struct device *dev)
/* Get the chip configuration */
config_t *config = dev->chip_info;
- int pwr_on=CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
+ int pwr_on = CONFIG_MAINBOARD_POWER_FAILURE_STATE;
int nmi_option;
/* BIOS must program... */
diff --git a/src/southbridge/intel/ibexpeak/Kconfig b/src/southbridge/intel/ibexpeak/Kconfig
index 7e2254e4d1..bb6e22cb73 100644
--- a/src/southbridge/intel/ibexpeak/Kconfig
+++ b/src/southbridge/intel/ibexpeak/Kconfig
@@ -38,6 +38,8 @@ config SOUTH_BRIDGE_OPTIONS # dummy
select INTEL_DESCRIPTOR_MODE_CAPABLE
select SOUTHBRIDGE_INTEL_COMMON_GPIO
select HAVE_INTEL_CHIPSET_LOCKDOWN
+ select HAVE_POWER_STATE_AFTER_FAILURE
+ select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE
config EHCI_BAR
hex
diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c
index 24a217d284..3358633792 100644
--- a/src/southbridge/intel/ibexpeak/lpc.c
+++ b/src/southbridge/intel/ibexpeak/lpc.c
@@ -174,7 +174,7 @@ static void pch_power_options(struct device *dev)
/* Get the chip configuration */
config_t *config = dev->chip_info;
- int pwr_on=CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
+ int pwr_on = CONFIG_MAINBOARD_POWER_FAILURE_STATE;
int nmi_option;
/* Which state do we want to goto after g3 (power restored)?
diff --git a/src/southbridge/intel/ibexpeak/pch.h b/src/southbridge/intel/ibexpeak/pch.h
index 35bf0caced..19add778f3 100644
--- a/src/southbridge/intel/ibexpeak/pch.h
+++ b/src/southbridge/intel/ibexpeak/pch.h
@@ -82,10 +82,6 @@ void southbridge_configure_default_intmap(void);
#define MAINBOARD_POWER_ON 1
#define MAINBOARD_POWER_KEEP 2
-#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
-#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON
-#endif
-
/* PCI Configuration Space (D30:F0): PCI2PCI */
#define PSTS 0x06
#define SMLT 0x1b
diff --git a/src/southbridge/intel/ibexpeak/smihandler.c b/src/southbridge/intel/ibexpeak/smihandler.c
index e510f19b6c..d305635398 100644
--- a/src/southbridge/intel/ibexpeak/smihandler.c
+++ b/src/southbridge/intel/ibexpeak/smihandler.c
@@ -403,7 +403,7 @@ static void southbridge_smi_sleep(void)
u8 reg8;
u32 reg32;
u8 slp_typ;
- u8 s5pwr = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
+ u8 s5pwr = CONFIG_MAINBOARD_POWER_FAILURE_STATE;
// save and recover RTC port values
u8 tmp70, tmp72;
diff --git a/src/southbridge/intel/lynxpoint/Kconfig b/src/southbridge/intel/lynxpoint/Kconfig
index e11bcef818..79f30ae706 100644
--- a/src/southbridge/intel/lynxpoint/Kconfig
+++ b/src/southbridge/intel/lynxpoint/Kconfig
@@ -39,6 +39,8 @@ config SOUTH_BRIDGE_OPTIONS # dummy
select SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ
select HAVE_INTEL_CHIPSET_LOCKDOWN
select COMMON_FADT
+ select HAVE_POWER_STATE_AFTER_FAILURE
+ select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE
config INTEL_LYNXPOINT_LP
bool
diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c
index 5b48da0848..10f57f543e 100644
--- a/src/southbridge/intel/lynxpoint/lpc.c
+++ b/src/southbridge/intel/lynxpoint/lpc.c
@@ -189,7 +189,7 @@ static void pch_power_options(struct device *dev)
/* Get the chip configuration */
config_t *config = dev->chip_info;
u16 pmbase = get_pmbase();
- int pwr_on=CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
+ int pwr_on = CONFIG_MAINBOARD_POWER_FAILURE_STATE;
int nmi_option;
/* Which state do we want to goto after g3 (power restored)?
diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h
index ee041d9dd2..2aa6b48785 100644
--- a/src/southbridge/intel/lynxpoint/pch.h
+++ b/src/southbridge/intel/lynxpoint/pch.h
@@ -210,10 +210,6 @@ void mainboard_config_superio(void);
#define MAINBOARD_POWER_ON 1
#define MAINBOARD_POWER_KEEP 2
-#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
-#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON
-#endif
-
/* PCI Configuration Space (D30:F0): PCI2PCI */
#define PSTS 0x06
#define SMLT 0x1b
diff --git a/src/southbridge/intel/lynxpoint/smihandler.c b/src/southbridge/intel/lynxpoint/smihandler.c
index 72298f3d91..fd1ba228a6 100644
--- a/src/southbridge/intel/lynxpoint/smihandler.c
+++ b/src/southbridge/intel/lynxpoint/smihandler.c
@@ -111,7 +111,7 @@ static void southbridge_smi_sleep(void)
u8 reg8;
u32 reg32;
u8 slp_typ;
- u8 s5pwr = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
+ u8 s5pwr = CONFIG_MAINBOARD_POWER_FAILURE_STATE;
u16 pmbase = get_pmbase();
// save and recover RTC port values
diff --git a/src/southbridge/nvidia/ck804/Kconfig b/src/southbridge/nvidia/ck804/Kconfig
index 338357e5e0..203890bf53 100644
--- a/src/southbridge/nvidia/ck804/Kconfig
+++ b/src/southbridge/nvidia/ck804/Kconfig
@@ -2,6 +2,7 @@ config SOUTHBRIDGE_NVIDIA_CK804
bool
select HAVE_USBDEBUG
select IOAPIC
+ select HAVE_POWER_STATE_AFTER_FAILURE
if SOUTHBRIDGE_NVIDIA_CK804
diff --git a/src/southbridge/nvidia/ck804/lpc.c b/src/southbridge/nvidia/ck804/lpc.c
index 2c7519b150..fe915eecc2 100644
--- a/src/southbridge/nvidia/ck804/lpc.c
+++ b/src/southbridge/nvidia/ck804/lpc.c
@@ -47,10 +47,6 @@
#define SLOW_CPU_OFF 0
#define SLOW_CPU__ON 1
-#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
-#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON
-#endif
-
static void lpc_common_init(struct device *dev)
{
u32 dword;
@@ -114,7 +110,7 @@ static void lpc_init(struct device *dev)
printk(BIOS_INFO, "%s: pm_base = %x\n", __func__, pm_base);
/* Power after power fail */
- on = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
+ on = CONFIG_MAINBOARD_POWER_FAILURE_STATE;
get_option(&on, "power_on_after_fail");
byte = pci_read_config8(dev, PREVIOUS_POWER_STATE);
byte &= ~0x45;
diff --git a/src/southbridge/nvidia/mcp55/Kconfig b/src/southbridge/nvidia/mcp55/Kconfig
index bb1b7df672..c70161e7ff 100644
--- a/src/southbridge/nvidia/mcp55/Kconfig
+++ b/src/southbridge/nvidia/mcp55/Kconfig
@@ -2,6 +2,7 @@ config SOUTHBRIDGE_NVIDIA_MCP55
bool
select HAVE_USBDEBUG
select IOAPIC
+ select HAVE_POWER_STATE_AFTER_FAILURE
if SOUTHBRIDGE_NVIDIA_MCP55
diff --git a/src/southbridge/nvidia/mcp55/lpc.c b/src/southbridge/nvidia/mcp55/lpc.c
index 3ac6464910..7e0fc89b69 100644
--- a/src/southbridge/nvidia/mcp55/lpc.c
+++ b/src/southbridge/nvidia/mcp55/lpc.c
@@ -48,10 +48,6 @@
#define SLOW_CPU_OFF 0
#define SLOW_CPU__ON 1
-#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
-#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON
-#endif
-
static void lpc_common_init(struct device *dev, int master)
{
u8 byte;
@@ -93,7 +89,7 @@ static void lpc_init(struct device *dev)
/* power after power fail */
#if 1
- on = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
+ on = CONFIG_MAINBOARD_POWER_FAILURE_STATE;
get_option(&on, "power_on_after_fail");
byte = pci_read_config8(dev, PREVIOUS_POWER_STATE);
byte &= ~0x40;