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| author | Sridhar Siricilla <sridhar.siricilla@intel.com> | 2019-09-13 16:32:00 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2020-08-13 05:44:24 +0000 |
| commit | b2353a7bdcaca6a6138e641ff1c5cfcbc7e6e799 (patch) | |
| tree | bfea012fdebc45bf5a8e079d05b0892c21ddc4ea /src/southbridge | |
| parent | 77025b3f56ab599db70e923650eb6e42d84f267f (diff) | |
| download | coreboot-b2353a7bdcaca6a6138e641ff1c5cfcbc7e6e799.tar.xz | |
soc/intel/common/block: Stitch CSE blobs into FW_MAIN_X partitions
Add Kconfig option for CSE me_rw blob path and stitch the me_rw blob
into FW_MAIN_X partitions.
BUG=b:145796136
Change-Id: I1d2908e9e16858c5f333e1b10b19d18b7ca27765
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35406
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge')
0 files changed, 0 insertions, 0 deletions