diff options
| author | Stefan Reinauer <stepan@coresystems.de> | 2010-03-22 11:42:32 +0000 |
|---|---|---|
| committer | Stefan Reinauer <stepan@openbios.org> | 2010-03-22 11:42:32 +0000 |
| commit | c02b4fc9db3c3c1e263027382697b566127f66bb (patch) | |
| tree | 11bd18488e360e5c1beeb9ccb852ef4489c3689a /src/southbridge | |
| parent | 27852aba6787617ca5656995cbc7e8ef0a3ea22c (diff) | |
| download | coreboot-c02b4fc9db3c3c1e263027382697b566127f66bb.tar.xz | |
printk_foo -> printk(BIOS_FOO, ...)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5266 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge')
138 files changed, 934 insertions, 936 deletions
diff --git a/src/southbridge/amd/amd8111/amd8111_acpi.c b/src/southbridge/amd/amd8111/amd8111_acpi.c index 67a789c08a..32e3808a98 100644 --- a/src/southbridge/amd/amd8111/amd8111_acpi.c +++ b/src/southbridge/amd/amd8111/amd8111_acpi.c @@ -79,7 +79,7 @@ static void acpi_init(struct device *dev) #if 0 uint16_t word; - printk_debug("ACPI: disabling NMI watchdog.. "); + printk(BIOS_DEBUG, "ACPI: disabling NMI watchdog.. "); byte = pci_read_config8(dev, 0x49); pci_write_config8(dev, 0x49, byte | (1<<2)); @@ -91,13 +91,13 @@ static void acpi_init(struct device *dev) byte = pci_read_config8(dev, 0x48); pci_write_config8(dev, 0x48, byte | (1<<3)); - printk_debug("done.\n"); + printk(BIOS_DEBUG, "done.\n"); - printk_debug("ACPI: Routing IRQ 12 to PS2 port.. "); + printk(BIOS_DEBUG, "ACPI: Routing IRQ 12 to PS2 port.. "); word = pci_read_config16(dev, 0x46); pci_write_config16(dev, 0x46, word | (1<<9)); - printk_debug("done.\n"); + printk(BIOS_DEBUG, "done.\n"); #endif /* To enable the register 0xcf9 in the IO space @@ -119,7 +119,7 @@ static void acpi_init(struct device *dev) byte |= 0x40; } pci_write_config8(dev, PREVIOUS_POWER_STATE, byte); - printk_info("set power %s after power fail\n", on?"on":"off"); + printk(BIOS_INFO, "set power %s after power fail\n", on?"on":"off"); /* switch serial irq logic from quiet mode to continuous * mode for Winbond W83627HF Rev. 17 @@ -135,13 +135,13 @@ static void acpi_init(struct device *dev) outl(((on<<1)+0x10) ,(pm10_bar + 0x10)); dword = inl(pm10_bar + 0x10); on = 8-on; - printk_debug("Throttling CPU %2d.%1.1d percent.\n", + printk(BIOS_DEBUG, "Throttling CPU %2d.%1.1d percent.\n", (on*12)+(on>>1),(on&1)*5); } #if CONFIG_GENERATE_ACPI_TABLES == 1 pm_base = pci_read_config16(dev, 0x58) & 0xff00; - printk_debug("pm_base: 0x%04x\n",pm_base); + printk(BIOS_DEBUG, "pm_base: 0x%04x\n",pm_base); #endif } diff --git a/src/southbridge/amd/amd8111/amd8111_ide.c b/src/southbridge/amd/amd8111/amd8111_ide.c index 6a1fd553b2..3b6f5a0a65 100644 --- a/src/southbridge/amd/amd8111/amd8111_ide.c +++ b/src/southbridge/amd/amd8111/amd8111_ide.c @@ -19,12 +19,12 @@ static void ide_init(struct device *dev) if (conf->ide1_enable) { /* Enable secondary ide interface */ word |= (1<<0); - printk_debug("IDE1 "); + printk(BIOS_DEBUG, "IDE1 "); } if (conf->ide0_enable) { /* Enable primary ide interface */ word |= (1<<1); - printk_debug("IDE0 "); + printk(BIOS_DEBUG, "IDE0 "); } word |= (1<<12); diff --git a/src/southbridge/amd/amd8111/amd8111_lpc.c b/src/southbridge/amd/amd8111/amd8111_lpc.c index edb32c240c..85e217bb65 100644 --- a/src/southbridge/amd/amd8111/amd8111_lpc.c +++ b/src/southbridge/amd/amd8111/amd8111_lpc.c @@ -22,7 +22,7 @@ static void enable_hpet(struct device *dev) pci_write_config32(dev,0xa0, 0xfed00001); hpet_address = pci_read_config32(dev,0xa0)& 0xfffffffe; - printk_debug("enabling HPET @0x%lx\n", hpet_address); + printk(BIOS_DEBUG, "enabling HPET @0x%lx\n", hpet_address); } diff --git a/src/southbridge/amd/amd8111/amd8111_nic.c b/src/southbridge/amd/amd8111/amd8111_nic.c index aa06253a46..8818b51b40 100644 --- a/src/southbridge/amd/amd8111/amd8111_nic.c +++ b/src/southbridge/amd/amd8111/amd8111_nic.c @@ -52,7 +52,7 @@ static void nic_init(struct device *dev) mmio = resource->base; /* Hard Reset PHY */ - printk_debug("Reseting PHY... "); + printk(BIOS_DEBUG, "Reseting PHY... "); if (conf->phy_lowreset) { write32((mmio + CMD3), VAL0 | PHY_RST_POL | RESET_PHY); } else { @@ -60,7 +60,7 @@ static void nic_init(struct device *dev) } mdelay(15); write32((mmio + CMD3), RESET_PHY); - printk_debug("Done\n"); + printk(BIOS_DEBUG, "Done\n"); } static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) diff --git a/src/southbridge/amd/amd8111/amd8111_usb2.c b/src/southbridge/amd/amd8111/amd8111_usb2.c index 0156b6ac2f..3aa5211dd0 100644 --- a/src/southbridge/amd/amd8111/amd8111_usb2.c +++ b/src/southbridge/amd/amd8111/amd8111_usb2.c @@ -26,7 +26,7 @@ static void amd8111_usb2_enable(device_t dev) // Due to buggy USB2 we force it to disable. dev->enabled = 0; amd8111_enable(dev); - printk_debug("USB2 disabled.\n"); + printk(BIOS_DEBUG, "USB2 disabled.\n"); } static struct device_operations usb2_ops = { diff --git a/src/southbridge/amd/amd8131/amd8131_bridge.c b/src/southbridge/amd/amd8131/amd8131_bridge.c index 29713a37c8..04930517e6 100644 --- a/src/southbridge/amd/amd8131/amd8131_bridge.c +++ b/src/southbridge/amd/amd8131/amd8131_bridge.c @@ -83,7 +83,7 @@ static void amd8131_pcix_tune_dev(device_t dev, void *ptr) } - printk_debug("%s AMD8131 PCI-X tuning\n", dev_path(dev)); + printk(BIOS_DEBUG, "%s AMD8131 PCI-X tuning\n", dev_path(dev)); status = pci_read_config32(dev, cap + PCI_X_STATUS); orig_cmd = cmd = pci_read_config16(dev,cap + PCI_X_CMD); @@ -170,7 +170,7 @@ static void amd8131_pcix_tune_dev(device_t dev, void *ptr) } } #if 0 - printk_debug("%s max_read: %d max_tran: %d sibs: %d sib_funcs: %d\n", + printk(BIOS_DEBUG, "%s max_read: %d max_tran: %d sibs: %d sib_funcs: %d\n", dev_path(dev), max_read, max_tran, sibs, sib_funcs, sib_funcs); #endif if (max_read != ((cmd & PCI_X_CMD_MAX_READ) >> 2)) { @@ -214,7 +214,7 @@ static unsigned int amd8131_scan_bus(struct bus *bus, info.sstatus = pci_read_config16(bus->dev, pos + PCI_X_SEC_STATUS); /* Print the PCI-X bus speed */ - printk_debug("PCI: %02x: %s\n", bus->secondary, pcix_speed(info.sstatus)); + printk(BIOS_DEBUG, "PCI: %02x: %s\n", bus->secondary, pcix_speed(info.sstatus)); /* Examine the bus and find out how loaded it is */ @@ -260,7 +260,7 @@ static unsigned int amd8131_scan_bus(struct bus *bus, * implement relaxed ordering. Errata #58 */ for(pbus = bus; !pbus->disable_relaxed_ordering; pbus = pbus->dev->bus) { - printk_spew("%s disabling relaxed ordering\n", + printk(BIOS_SPEW, "%s disabling relaxed ordering\n", bus_path(pbus)); pbus->disable_relaxed_ordering = 1; } diff --git a/src/southbridge/amd/amd8132/amd8132_bridge.c b/src/southbridge/amd/amd8132/amd8132_bridge.c index 8dc57d4510..2c18c5ebcb 100644 --- a/src/southbridge/amd/amd8132/amd8132_bridge.c +++ b/src/southbridge/amd/amd8132/amd8132_bridge.c @@ -107,7 +107,7 @@ static void amd8132_pcix_tune_dev(device_t dev, void *ptr) /* How many siblings does this device have? */ sibs = info->master_devices - 1; - printk_debug("%s AMD8132 PCI-X tuning\n", dev_path(dev)); + printk(BIOS_DEBUG, "%s AMD8132 PCI-X tuning\n", dev_path(dev)); status = pci_read_config32(dev, cap + PCI_X_STATUS); orig_cmd = cmd = pci_read_config16(dev,cap + PCI_X_CMD); @@ -177,7 +177,7 @@ static unsigned int amd8132_scan_bus(struct bus *bus, info.sstatus = pci_read_config16(bus->dev, pos + PCI_X_SEC_STATUS); /* Print the PCI-X bus speed */ - printk_debug("PCI: %02x: %s sstatus=%04x rev=%02x \n", bus->secondary, pcix_speed(info.sstatus), info.sstatus, info.rev); + printk(BIOS_DEBUG, "PCI: %02x: %s sstatus=%04x rev=%02x \n", bus->secondary, pcix_speed(info.sstatus), info.sstatus, info.rev); /* Examine the bus and find out how loaded it is */ diff --git a/src/southbridge/amd/cs5530/cs5530_ide.c b/src/southbridge/amd/cs5530/cs5530_ide.c index 09906b78bc..a1fa2dc2c3 100644 --- a/src/southbridge/amd/cs5530/cs5530_ide.c +++ b/src/southbridge/amd/cs5530/cs5530_ide.c @@ -55,9 +55,9 @@ static void ide_init(struct device *dev) pci_write_config8(dev, DECODE_CONTROL_REG2, reg8); - printk_info("%s IDE interface %s\n", "Primary", + printk(BIOS_INFO, "%s IDE interface %s\n", "Primary", conf->ide0_enable ? "enabled" : "disabled"); - printk_info("%s IDE interface %s\n", "Secondary", + printk(BIOS_INFO, "%s IDE interface %s\n", "Secondary", conf->ide1_enable ? "enabled" : "disabled"); } diff --git a/src/southbridge/amd/cs5530/cs5530_vga.c b/src/southbridge/amd/cs5530/cs5530_vga.c index 9347a081b8..2a2a8d8bdf 100644 --- a/src/southbridge/amd/cs5530/cs5530_vga.c +++ b/src/southbridge/amd/cs5530/cs5530_vga.c @@ -460,7 +460,7 @@ static void cs5530_vga_init(device_t dev) gx_base = GX_BASE; mode = modes[CONFIG_GX1_VIDEOMODE]; - printk_debug("Setting up video mode %dx%d with %d Hz clock\n", + printk(BIOS_DEBUG, "Setting up video mode %dx%d with %d Hz clock\n", mode->visible_pixel, mode->visible_lines, mode->pixel_clock); cs5530_set_clock_frequency(io_base, mode->pll_value); diff --git a/src/southbridge/amd/cs5535/cs5535.c b/src/southbridge/amd/cs5535/cs5535.c index 17bd902e0b..6f203558e3 100644 --- a/src/southbridge/amd/cs5535/cs5535.c +++ b/src/southbridge/amd/cs5535/cs5535.c @@ -39,14 +39,14 @@ static void nvram_on(struct device *dev) *flash = 0xf0; - printk_debug("Flash device: MFGID %02x, DEVID %02x\n", id1, id2); + printk(BIOS_DEBUG, "Flash device: MFGID %02x, DEVID %02x\n", id1, id2); #endif } static void southbridge_init(struct device *dev) { - printk_spew("cs5535: %s\n", __func__); + printk(BIOS_SPEW, "cs5535: %s\n", __func__); nvram_on(dev); } @@ -56,17 +56,17 @@ static void dump_south(struct device *dev) int i, j; for(i=0; i<256; i+=16) { - printk_debug("0x%02x: ", i); + printk(BIOS_DEBUG, "0x%02x: ", i); for(j=0; j<16; j++) - printk_debug("%02x ", pci_read_config8(dev, i+j)); - printk_debug("\n"); + printk(BIOS_DEBUG, "%02x ", pci_read_config8(dev, i+j)); + printk(BIOS_DEBUG, "\n"); } } */ static void southbridge_enable(struct device *dev) { - printk_spew("%s: dev is %p\n", __func__, dev); + printk(BIOS_SPEW, "%s: dev is %p\n", __func__, dev); } static void cs5535_read_resources(device_t dev) @@ -89,7 +89,7 @@ static void cs5535_read_resources(device_t dev) static void cs5535_pci_dev_enable_resources(device_t dev) { - printk_spew("cs5535.c: %s()\n", __func__); + printk(BIOS_SPEW, "cs5535.c: %s()\n", __func__); pci_dev_enable_resources(dev); enable_childrens_resources(dev); } diff --git a/src/southbridge/amd/cs5535/cs5535_ide.c b/src/southbridge/amd/cs5535/cs5535_ide.c index 30901672b7..b997ca2463 100644 --- a/src/southbridge/amd/cs5535/cs5535_ide.c +++ b/src/southbridge/amd/cs5535/cs5535_ide.c @@ -7,12 +7,12 @@ static void ide_init(struct device *dev) { - printk_spew("cs5535_ide: %s\n", __func__); + printk(BIOS_SPEW, "cs5535_ide: %s\n", __func__); } static void ide_enable(struct device *dev) { - printk_spew("cs5535_ide: %s\n", __func__); + printk(BIOS_SPEW, "cs5535_ide: %s\n", __func__); } static struct device_operations ide_ops = { diff --git a/src/southbridge/amd/cs5536/cs5536.c b/src/southbridge/amd/cs5536/cs5536.c index e974d399d1..f068006f75 100644 --- a/src/southbridge/amd/cs5536/cs5536.c +++ b/src/southbridge/amd/cs5536/cs5536.c @@ -155,10 +155,10 @@ static void ChipsetFlashSetup(void) int i; int numEnabled = 0; - printk_debug("ChipsetFlashSetup: Start\n"); + printk(BIOS_DEBUG, "ChipsetFlashSetup: Start\n"); for (i = 0; i < FlashInitTableLen; i++) { if (FlashInitTable[i].fType != FLASH_TYPE_NONE) { - printk_debug("Enable CS%d\n", i); + printk(BIOS_DEBUG, "Enable CS%d\n", i); /* we need to configure the memory/IO mask */ msr = rdmsr(FlashPort[i]); msr.hi = 0; /* start with the "enabled" bit clear */ @@ -171,14 +171,14 @@ static void ChipsetFlashSetup(void) else msr.hi &= ~0x00000004; msr.hi |= FlashInitTable[i].fMask; - printk_debug("MSR(0x%08X, %08X_%08X)\n", FlashPort[i], + printk(BIOS_DEBUG, "MSR(0x%08X, %08X_%08X)\n", FlashPort[i], msr.hi, msr.lo); wrmsr(FlashPort[i], msr); /* now write-enable the device */ msr = rdmsr(MDD_NORF_CNTRL); msr.lo |= (1 << i); - printk_debug("MSR(0x%08X, %08X_%08X)\n", MDD_NORF_CNTRL, + printk(BIOS_DEBUG, "MSR(0x%08X, %08X_%08X)\n", MDD_NORF_CNTRL, msr.hi, msr.lo); wrmsr(MDD_NORF_CNTRL, msr); @@ -187,7 +187,7 @@ static void ChipsetFlashSetup(void) } } - printk_debug("ChipsetFlashSetup: Finish\n"); + printk(BIOS_DEBUG, "ChipsetFlashSetup: Finish\n"); } @@ -566,7 +566,7 @@ void chipsetinit(void) } /* Flash BAR size Setup */ - printk_err("%sDoing ChipsetFlashSetup()\n", + printk(BIOS_ERR, "%sDoing ChipsetFlashSetup()\n", sb->enable_ide_nand_flash == 1 ? "" : "Not "); if (sb->enable_ide_nand_flash == 1) ChipsetFlashSetup(); @@ -594,7 +594,7 @@ static void southbridge_init(struct device *dev) * unsigned short gpiobase = MDD_GPIO; */ - printk_err("cs5536: %s\n", __func__); + printk(BIOS_ERR, "cs5536: %s\n", __func__); setup_i8259(); lpc_init(sb); uarts_init(sb); @@ -606,7 +606,7 @@ static void southbridge_init(struct device *dev) (sb->enable_gpio_int_route >> 16)); } - printk_err("cs5536: %s: enable_ide_nand_flash is %d\n", __func__, + printk(BIOS_ERR, "cs5536: %s: enable_ide_nand_flash is %d\n", __func__, sb->enable_ide_nand_flash); if (sb->enable_ide_nand_flash == 1) { enable_ide_nand_flash_header(); @@ -616,7 +616,7 @@ static void southbridge_init(struct device *dev) /* disable unwanted virtual PCI devices */ for (i = 0; (i < MAX_UNWANTED_VPCI) && (0 != sb->unwanted_vpci[i]); i++) { - printk_debug("Disabling VPCI device: 0x%08X\n", + printk(BIOS_DEBUG, "Disabling VPCI device: 0x%08X\n", sb->unwanted_vpci[i]); outl(sb->unwanted_vpci[i] + 0x7C, 0xCF8); outl(0xDEADBEEF, 0xCFC); @@ -644,13 +644,13 @@ static void cs5536_read_resources(device_t dev) static void southbridge_enable(struct device *dev) { - printk_err("cs5536: %s: dev is %p\n", __func__, dev); + printk(BIOS_ERR, "cs5536: %s: dev is %p\n", __func__, dev); } static void cs5536_pci_dev_enable_resources(device_t dev) { - printk_err("cs5536: %s()\n", __func__); + printk(BIOS_ERR, "cs5536: %s()\n", __func__); pci_dev_enable_resources(dev); enable_childrens_resources(dev); } diff --git a/src/southbridge/amd/cs5536/cs5536_early_smbus.c b/src/southbridge/amd/cs5536/cs5536_early_smbus.c index e5a133e903..298feeed9b 100644 --- a/src/southbridge/amd/cs5536/cs5536_early_smbus.c +++ b/src/southbridge/amd/cs5536/cs5536_early_smbus.c @@ -53,7 +53,7 @@ static int smbus_wait(unsigned smbus_io_base) if ((val & SMB_STS_SDAST) != 0) break; if (val & (SMB_STS_BER | SMB_STS_NEGACK)) { - /*printk_debug("SMBUS WAIT ERROR %x\n", val); */ + /*printk(BIOS_DEBUG, "SMBUS WAIT ERROR %x\n", val); */ return SMBUS_ERROR; } } while (--loops); @@ -123,7 +123,7 @@ static int smbus_send_slave_address(unsigned smbus_io_base, /* check for bus conflict and NACK */ val = inb(smbus_io_base + SMB_STS); if (((val & SMB_STS_BER) != 0) || ((val & SMB_STS_NEGACK) != 0)) { - /* printk_debug("SEND SLAVE ERROR (%x)\n", val); */ + /* printk(BIOS_DEBUG, "SEND SLAVE ERROR (%x)\n", val); */ return SMBUS_ERROR; } return smbus_wait(smbus_io_base); diff --git a/src/southbridge/amd/cs5536/cs5536_ide.c b/src/southbridge/amd/cs5536/cs5536_ide.c index bbb6bb5bcd..4acf3ed61a 100644 --- a/src/southbridge/amd/cs5536/cs5536_ide.c +++ b/src/southbridge/amd/cs5536/cs5536_ide.c @@ -36,7 +36,7 @@ static void ide_init(struct device *dev) { uint32_t ide_cfg; - printk_spew("cs5536_ide: %s\n", __func__); + printk(BIOS_SPEW, "cs5536_ide: %s\n", __func__); /* GPIO and IRQ setup are handled in the main chipset code. */ // Enable the channel and Post Write Buffer @@ -49,7 +49,7 @@ static void ide_init(struct device *dev) static void ide_enable(struct device *dev) { - printk_spew("cs5536_ide: %s\n", __func__); + printk(BIOS_SPEW, "cs5536_ide: %s\n", __func__); } diff --git a/src/southbridge/amd/cs5536/cs5536_smbus2.h b/src/southbridge/amd/cs5536/cs5536_smbus2.h index 3b9e96c485..a470b3714c 100644 --- a/src/southbridge/amd/cs5536/cs5536_smbus2.h +++ b/src/southbridge/amd/cs5536/cs5536_smbus2.h @@ -78,7 +78,7 @@ static int smbus_wait(unsigned smbus_io_base) if ((val & SMB_STS_SDAST) != 0) break; if (val & (SMB_STS_BER | SMB_STS_NEGACK)) { - printk_debug("SMBUS WAIT ERROR %x\n", val); + printk(BIOS_DEBUG, "SMBUS WAIT ERROR %x\n", val); return SMBUS_ERROR; } } while (--loops); @@ -171,7 +171,7 @@ static int smbus_send_slave_address(unsigned smbus_io_base, /* check for bus conflict and NACK */ val = inb(smbus_io_base + SMB_STS); if (((val & SMB_STS_BER) != 0) || ((val & SMB_STS_NEGACK) != 0)) { - printk_debug("SEND SLAVE ERROR (%x)\n", val); + printk(BIOS_DEBUG, "SEND SLAVE ERROR (%x)\n", val); return SMBUS_ERROR; } return smbus_wait(smbus_io_base); @@ -250,7 +250,7 @@ static void _doread(unsigned smbus_io_base, unsigned char device, return; err: - printk_debug("SMBUS READ ERROR (%d): %d\n", index, ret); + printk(BIOS_DEBUG, "SMBUS READ ERROR (%d): %d\n", index, ret); } static unsigned char do_smbus_read_byte(unsigned smbus_io_base, @@ -300,7 +300,7 @@ static int _dowrite(unsigned smbus_io_base, unsigned char device, return 0; err: - printk_debug("SMBUS WRITE ERROR: %d\n", ret); + printk(BIOS_DEBUG, "SMBUS WRITE ERROR: %d\n", ret); return -1; } diff --git a/src/southbridge/amd/rs690/rs690.c b/src/southbridge/amd/rs690/rs690.c index 40913b3388..caf838aacf 100644 --- a/src/southbridge/amd/rs690/rs690.c +++ b/src/southbridge/amd/rs690/rs690.c @@ -129,7 +129,7 @@ void rs690_enable(device_t dev) device_t nb_dev = 0, sb_dev = 0; int dev_ind; - printk_info("rs690_enable: dev=%p, VID_DID=0x%x\n", dev, get_vid_did(dev)); + printk(BIOS_INFO, "rs690_enable: dev=%p, VID_DID=0x%x\n", dev, get_vid_did(dev)); nb_dev = dev_find_slot(0, PCI_DEVFN(0, 0)); if (!nb_dev) { @@ -147,7 +147,7 @@ void rs690_enable(device_t dev) dev_ind = dev->path.pci.devfn >> 3; switch (dev_ind) { case 0: /* bus0, dev0, fun0; */ - printk_info("Bus-0, Dev-0, Fun-0.\n"); + printk(BIOS_INFO, "Bus-0, Dev-0, Fun-0.\n"); enable_pcie_bar3(nb_dev); /* PCIEMiscInit */ config_gpp_core(nb_dev, sb_dev); rs690_gpp_sb_init(nb_dev, sb_dev, 8); @@ -159,11 +159,11 @@ void rs690_enable(device_t dev) break; case 1: /* bus0, dev1 */ - printk_info("Bus-0, Dev-1, Fun-0.\n"); + printk(BIOS_INFO, "Bus-0, Dev-1, Fun-0.\n"); break; case 2: /* bus0, dev2,3, two GFX */ case 3: - printk_info("Bus-0, Dev-2,3, Fun-0. enable=%d\n", dev->enabled); + printk(BIOS_INFO, "Bus-0, Dev-2,3, Fun-0. enable=%d\n", dev->enabled); set_nbmisc_enable_bits(nb_dev, 0x0c, 1 << dev_ind, (dev->enabled ? 0 : 1) << dev_ind); if (dev->enabled) @@ -173,7 +173,7 @@ void rs690_enable(device_t dev) case 5: case 6: case 7: - printk_info("Bus-0, Dev-4,5,6,7, Fun-0. enable=%d\n", + printk(BIOS_INFO, "Bus-0, Dev-4,5,6,7, Fun-0. enable=%d\n", dev->enabled); set_nbmisc_enable_bits(nb_dev, 0x0c, 1 << dev_ind, (dev->enabled ? 0 : 1) << dev_ind); @@ -181,7 +181,7 @@ void rs690_enable(device_t dev) rs690_gpp_sb_init(nb_dev, dev, dev_ind); break; case 8: /* bus0, dev8, SB */ - printk_info("Bus-0, Dev-8, Fun-0. enable=%d\n", dev->enabled); + printk(BIOS_INFO, "Bus-0, Dev-8, Fun-0. enable=%d\n", dev->enabled); set_nbmisc_enable_bits(nb_dev, 0x00, 1 << 6, (dev->enabled ? 1 : 0) << 6); if (dev->enabled) @@ -189,7 +189,7 @@ void rs690_enable(device_t dev) disable_pcie_bar3(nb_dev); break; default: - printk_debug("unknown dev: %s\n", dev_path(dev)); + printk(BIOS_DEBUG, "unknown dev: %s\n", dev_path(dev)); } } diff --git a/src/southbridge/amd/rs690/rs690_cmn.c b/src/southbridge/amd/rs690/rs690_cmn.c index aa75a64f4f..026341394a 100644 --- a/src/southbridge/amd/rs690/rs690_cmn.c +++ b/src/southbridge/amd/rs690/rs690_cmn.c @@ -50,7 +50,7 @@ u32 pci_ext_read_config32(device_t nb_dev, device_t dev, u32 reg) { /*get BAR3 base address for nbcfg0x1c */ u32 addr = pci_read_config32(nb_dev, 0x1c) & ~0xF; - printk_debug("addr=%x,bus=%x,devfn=%x\n", addr, dev->bus->secondary, + printk(BIOS_DEBUG, "addr=%x,bus=%x,devfn=%x\n", addr, dev->bus->secondary, dev->path.pci.devfn); addr |= dev->bus->secondary << 20 | /* bus num */ dev->path.pci.devfn << 12 | reg; @@ -63,7 +63,7 @@ void pci_ext_write_config32(device_t nb_dev, device_t dev, u32 reg_pos, u32 mask /*get BAR3 base address for nbcfg0x1c */ u32 addr = pci_read_config32(nb_dev, 0x1c) & ~0xF; - /*printk_debug("write: addr=%x,bus=%x,devfn=%x\n", addr, dev->bus->secondary, + /*printk(BIOS_DEBUG, "write: addr=%x,bus=%x,devfn=%x\n", addr, dev->bus->secondary, dev->path.pci.devfn);*/ addr |= dev->bus->secondary << 20 | /* bus num */ dev->path.pci.devfn << 12 | reg_pos; @@ -253,7 +253,7 @@ u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port) mdelay(40); udelay(200); lc_state = nbpcie_p_read_index(dev, 0xa5); /* lc_state */ - printk_debug("PcieLinkTraining port=%x:lc current state=%x\n", + printk(BIOS_DEBUG, "PcieLinkTraining port=%x:lc current state=%x\n", port, lc_state); current = lc_state & 0x3f; /* get LC_CURRENT_STATE, bit0-5 */ @@ -274,7 +274,7 @@ u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port) reg = pci_ext_read_config32(nb_dev, dev, PCIE_VC0_RESOURCE_STATUS); - printk_debug("PcieTrainPort reg=0x%x\n", reg); + printk(BIOS_DEBUG, "PcieTrainPort reg=0x%x\n", reg); /* check bit1 */ if (reg & VC_NEGOTIATION_PENDING) { /* bit1=1 means the link needs to be re-trained. */ /* set bit8=1, bit0-2=bit4-6 */ diff --git a/src/southbridge/amd/rs690/rs690_early_setup.c b/src/southbridge/amd/rs690/rs690_early_setup.c index d253f0d868..5afb7b57a3 100644 --- a/src/southbridge/amd/rs690/rs690_early_setup.c +++ b/src/southbridge/amd/rs690/rs690_early_setup.c @@ -133,23 +133,23 @@ static void get_cpu_rev() u32 eax, ebx, ecx, edx; __asm__ volatile ("cpuid":"=a" (eax), "=b"(ebx), "=c"(ecx), "=d"(edx) :"0"(1)); - printk_info("get_cpu_rev EAX=0x%x.\n", eax); + printk(BIOS_INFO, "get_cpu_rev EAX=0x%x.\n", eax); if (eax <= 0xfff) - printk_info("CPU Rev is K8_Cx.\n"); + printk(BIOS_INFO, "CPU Rev is K8_Cx.\n"); else if (eax <= 0x10fff) - printk_info("CPU Rev is K8_Dx.\n"); + printk(BIOS_INFO, "CPU Rev is K8_Dx.\n"); else if (eax <= 0x20fff) - printk_info("CPU Rev is K8_Ex.\n"); + printk(BIOS_INFO, "CPU Rev is K8_Ex.\n"); else if (eax <= 0x40fff) - printk_info("CPU Rev is K8_Fx.\n"); + printk(BIOS_INFO, "CPU Rev is K8_Fx.\n"); else if (eax == 0x60fb1 || eax == 0x60f81) /*These two IDS are exception, they are G1. */ - printk_info("CPU Rev is K8_G1.\n"); + printk(BIOS_INFO, "CPU Rev is K8_G1.\n"); else if (eax <= 0X60FF0) - printk_info("CPU Rev is K8_G0.\n"); + printk(BIOS_INFO, "CPU Rev is K8_G0.\n"); else if (eax <= 0x100000) - printk_info("CPU Rev is K8_G1.\n"); + printk(BIOS_INFO, "CPU Rev is K8_G1.\n"); else - printk_info("CPU Rev is K8_10.\n"); + printk(BIOS_INFO, "CPU Rev is K8_10.\n"); } static u8 get_nb_rev(device_t nb_dev) @@ -197,19 +197,19 @@ static void rs690_htinit() ************************/ reg = pci_read_config32(k8_f0, 0x88); k8_ht_freq = (reg & 0xf00) >> 8; - printk_spew("rs690_htinit k8_ht_freq=%x.\n", k8_ht_freq); + printk(BIOS_SPEW, "rs690_htinit k8_ht_freq=%x.\n", k8_ht_freq); rs690_f0 = PCI_DEV(0, 0, 0); reg8 = pci_read_config8(rs690_f0, 0x9c); - printk_spew("rs690_htinit NB_CFG_Q_F1000_800=%x\n", reg8); + printk(BIOS_SPEW, "rs690_htinit NB_CFG_Q_F1000_800=%x\n", reg8); /* For 1000 MHz HT, NB_CFG_Q_F1000_800 bit 0 MUST be set. * For any other HT frequency, NB_CFG_Q_F1000_800 bit 0 MUST NOT be set. */ if (((k8_ht_freq == 0x6) || (k8_ht_freq == 0xf)) && (!(reg8 & 0x1))) { - printk_info("rs690_htinit setting bit 0 in NB_CFG_Q_F1000_800 to use 1 GHz HT\n"); + printk(BIOS_INFO, "rs690_htinit setting bit 0 in NB_CFG_Q_F1000_800 to use 1 GHz HT\n"); reg8 |= 0x1; pci_write_config8(rs690_f0, 0x9c, reg8); } else if ((k8_ht_freq != 0x6) && (k8_ht_freq != 0xf) && (reg8 & 0x1)) { - printk_info("rs690_htinit clearing bit 0 in NB_CFG_Q_F1000_800 to not use 1 GHz HT\n"); + printk(BIOS_INFO, "rs690_htinit clearing bit 0 in NB_CFG_Q_F1000_800 to not use 1 GHz HT\n"); reg8 &= ~0x1; pci_write_config8(rs690_f0, 0x9c, reg8); } @@ -234,7 +234,7 @@ static void k8_optimization() device_t k8_f0, k8_f2, k8_f3; msr_t msr; - printk_info("k8_optimization()\n"); + printk(BIOS_INFO, "k8_optimization()\n"); k8_f0 = PCI_DEV(0, 0x18, 0); k8_f2 = PCI_DEV(0, 0x18, 2); k8_f3 = PCI_DEV(0, 0x18, 3); @@ -425,7 +425,7 @@ static void rs690_por_htiu_index_init(device_t nb_dev) *****************************************/ static void rs690_por_init(device_t nb_dev) { - printk_info("rs690_por_init\n"); + printk(BIOS_INFO, "rs690_por_init\n"); /* ATINB_PCICFG_POR_TABLE, initialize the values for rs690 PCI Config registers */ rs690_por_pcicfg_init(nb_dev); @@ -463,19 +463,19 @@ static void rs690_before_pci_init() static void rs690_early_setup() { device_t nb_dev = PCI_DEV(0, 0, 0); - printk_info("rs690_early_setup()\n"); + printk(BIOS_INFO, "rs690_early_setup()\n"); /*ATINB_PrepareInit */ get_cpu_rev(); switch (get_nb_rev(nb_dev)) { /* PCIEMiscInit */ case 5: - printk_info("NB Revision is A11.\n"); + printk(BIOS_INFO, "NB Revision is A11.\n"); break; case 6: - printk_info("NB Revision is A12.\n"); + printk(BIOS_INFO, "NB Revision is A12.\n"); break; case 7: - printk_info("NB Revision is A21.\n"); + printk(BIOS_INFO, "NB Revision is A21.\n"); break; } diff --git a/src/southbridge/amd/rs690/rs690_gfx.c b/src/southbridge/amd/rs690/rs690_gfx.c index 3c87fa0447..7f76a057ac 100644 --- a/src/southbridge/amd/rs690/rs690_gfx.c +++ b/src/southbridge/amd/rs690/rs690_gfx.c @@ -45,7 +45,7 @@ static u32 clkind_read(device_t dev, u32 index) static void clkind_write(device_t dev, u32 index, u32 data) { u32 gfx_bar2 = pci_read_config32(dev, 0x18) & ~0xF; - /* printk_info("gfx bar 2 %02x\n", gfx_bar2); */ + /* printk(BIOS_INFO, "gfx bar 2 %02x\n", gfx_bar2); */ *(u32*)(gfx_bar2+CLK_CNTL_INDEX) = index | 1<<7; *(u32*)(gfx_bar2+CLK_CNTL_DATA) = data; @@ -57,7 +57,7 @@ static void clkind_write(device_t dev, u32 index, u32 data) */ static void rs690_gfx_read_resources(device_t dev) { - printk_info("rs690_gfx_read_resources.\n"); + printk(BIOS_INFO, "rs690_gfx_read_resources.\n"); /* The initial value of 0x24 is 0xFFFFFFFF, which is confusing. Even if we write 0xFFFFFFFF into it, it will be 0xFFF00000, @@ -77,7 +77,7 @@ static void internal_gfx_pci_dev_init(struct device *dev) (struct southbridge_amd_rs690_config *)dev->chip_info; deviceid = pci_read_config16(dev, PCI_DEVICE_ID); vendorid = pci_read_config16(dev, PCI_VENDOR_ID); - printk_info("internal_gfx_pci_dev_init device=%x, vendor=%x.\n", + printk(BIOS_INFO, "internal_gfx_pci_dev_init device=%x, vendor=%x.\n", deviceid, vendorid); pci_dev_init(dev); @@ -117,12 +117,12 @@ static void rs690_internal_gfx_enable(device_t dev) device_t k8_f0 = 0, k8_f2 = 0; device_t nb_dev = dev_find_slot(0, 0); - printk_info("rs690_internal_gfx_enable dev=0x%p, nb_dev=0x%p.\n", dev, + printk(BIOS_INFO, "rs690_internal_gfx_enable dev=0x%p, nb_dev=0x%p.\n", dev, nb_dev); /* set APERTURE_SIZE, 128M. */ l_dword = pci_read_config32(nb_dev, 0x8c); - printk_info("nb_dev, 0x8c=0x%x\n", l_dword); + printk(BIOS_INFO, "nb_dev, 0x8c=0x%x\n", l_dword); l_dword &= 0xffffff8f; pci_write_config32(nb_dev, 0x8c, l_dword); @@ -231,13 +231,13 @@ static void single_port_configuration(device_t nb_dev, device_t dev) struct southbridge_amd_rs690_config *cfg = (struct southbridge_amd_rs690_config *)nb_dev->chip_info; - printk_info("rs690_gfx_init single_port_configuration.\n"); + printk(BIOS_INFO, "rs690_gfx_init single_port_configuration.\n"); /* step 12 training, releases hold training for GFX port 0 (device 2) */ set_nbmisc_enable_bits(nb_dev, 0x8, 1 << 4, 0<<4); PcieReleasePortTraining(nb_dev, dev, 2); result = PcieTrainPort(nb_dev, dev, 2); - printk_info("rs690_gfx_init single_port_configuration step12.\n"); + printk(BIOS_INFO, "rs690_gfx_init single_port_configuration step12.\n"); /* step 13 Power Down Control */ /* step 13.1 Enables powering down transmitter and receiver pads along with PLL macros. */ @@ -257,7 +257,7 @@ static void single_port_configuration(device_t nb_dev, device_t dev) reg32 = nbpcie_p_read_index(dev, 0xa2); width = (reg32 >> 4) & 0x7; - printk_debug("GFX LC_LINK_WIDTH = 0x%x.\n", width); + printk(BIOS_DEBUG, "GFX LC_LINK_WIDTH = 0x%x.\n", width); switch (width) { case 1: case 2: @@ -274,11 +274,11 @@ static void single_port_configuration(device_t nb_dev, device_t dev) break; } } - printk_info("rs690_gfx_init single_port_configuration step13.\n"); + printk(BIOS_INFO, "rs690_gfx_init single_port_configuration step13.\n"); /* step 14 Reset Enumeration Timer, disables the shortening of the enumeration timer */ set_pcie_enable_bits(dev, 0x70, 1 << 19, 0 << 19); - printk_info("rs690_gfx_init single_port_configuration step14.\n"); + printk(BIOS_INFO, "rs690_gfx_init single_port_configuration step14.\n"); } /* step 15 ~ step 18 from rpr */ @@ -305,7 +305,7 @@ static void dual_port_configuration(device_t nb_dev, device_t dev) reg32 = nbpcie_p_read_index(dev, 0xa2); width = (reg32 >> 4) & 0x7; - printk_debug("GFX LC_LINK_WIDTH = 0x%x.\n", width); + printk(BIOS_DEBUG, "GFX LC_LINK_WIDTH = 0x%x.\n", width); switch (width) { case 1: case 2: @@ -335,7 +335,7 @@ static void dual_port_configuration(device_t nb_dev, device_t dev) reg32 = nbpcie_p_read_index(dev, 0xa2); width = (reg32 >> 4) & 0x7; - printk_debug("GFX LC_LINK_WIDTH = 0x%x.\n", width); + printk(BIOS_DEBUG, "GFX LC_LINK_WIDTH = 0x%x.\n", width); switch (width) { case 1: case 2: @@ -413,13 +413,13 @@ void rs690_gfx_init(device_t nb_dev, device_t dev, u32 port) struct southbridge_amd_rs690_config *cfg = (struct southbridge_amd_rs690_config *)nb_dev->chip_info; - printk_info("rs690_gfx_init, nb_dev=0x%p, dev=0x%p, port=0x%x.\n", + printk(BIOS_INFO, "rs690_gfx_init, nb_dev=0x%p, dev=0x%p, port=0x%x.\n", nb_dev, dev, port); /* step 0, REFCLK_SEL, skip A11 revision */ set_nbmisc_enable_bits(nb_dev, 0x6a, 1 << 9, cfg->gfx_dev2_dev3 ? 1 << 9 : 0 << 9); - printk_info("rs690_gfx_init step0.\n"); + printk(BIOS_INFO, "rs690_gfx_init step0.\n"); /* step 1, lane reversal (only need if CMOS option is enabled) */ if (cfg->gfx_lane_reversal) { @@ -427,13 +427,13 @@ void rs690_gfx_init(device_t nb_dev, device_t dev, u32 port) if (cfg->gfx_dual_slot) set_nbmisc_enable_bits(nb_dev, 0x33, 1 << 3, 1 << 3); } - printk_info("rs690_gfx_init step1.\n"); + printk(BIOS_INFO, "rs690_gfx_init step1.\n"); /* step 1.1, dual-slot gfx configuration (only need if CMOS option is enabled) */ /* AMD calls the configuration CrossFire */ if (cfg->gfx_dual_slot) set_nbmisc_enable_bits(nb_dev, 0x0, 0xf << 8, 5 << 8); - printk_info("rs690_gfx_init step2.\n"); + printk(BIOS_INFO, "rs690_gfx_init step2.\n"); /* step 2, TMDS, (only need if CMOS option is enabled) */ if (cfg->gfx_tmds) { @@ -461,7 +461,7 @@ void rs690_gfx_init(device_t nb_dev, device_t dev, u32 port) /* step 4.6 bring external GFX device out of reset, wait for 1ms */ mdelay(1); - printk_info("rs690_gfx_init step4.\n"); + printk(BIOS_INFO, "rs690_gfx_init step4.\n"); /* step 5 program PCIE memory mapped configuration space */ /* done by enable_pci_bar3() before */ @@ -508,7 +508,7 @@ void rs690_gfx_init(device_t nb_dev, device_t dev, u32 port) set_nbmisc_enable_bits(nb_dev, 0x35, 0x3 << 2, 0x3 << 2); } - printk_info("rs690_gfx_init step6.\n"); + printk(BIOS_INFO, "rs690_gfx_init step6.\n"); /* step 7 compliance state, (only need if CMOS option is enabled) */ /* the compliance stete is just for test. refer to 4.2.5.2 of PCIe specification */ @@ -518,64 +518,64 @@ void rs690_gfx_init(device_t nb_dev, device_t dev, u32 port) /* release hold training for device 2. GFX initialization is done. */ set_nbmisc_enable_bits(nb_dev, 0x8, 1 << 4, 0 << 4); dynamic_link_width_control(nb_dev, dev, cfg->gfx_link_width); - printk_info("rs690_gfx_init step7.\n"); + printk(BIOS_INFO, "rs690_gfx_init step7.\n"); return; } /* step 8 common initialization */ /* step 8.1 sets RCB timeout to be 25ms */ set_pcie_enable_bits(dev, 0x70, 7 << 16, 3 << 16); - printk_info("rs690_gfx_init step8.1.\n"); + printk(BIOS_INFO, "rs690_gfx_init step8.1.\n"); /* step 8.2 disables slave ordering logic */ set_pcie_enable_bits(nb_dev, 0x20, 1 << 8, 1 << 8); - printk_info("rs690_gfx_init step8.2.\n"); + printk(BIOS_INFO, "rs690_gfx_init step8.2.\n"); /* step 8.3 sets DMA payload size to 64 bytes */ set_pcie_enable_bits(nb_dev, 0x10, 7 << 10, 4 << 10); - printk_info("rs690_gfx_init step8.3.\n"); + printk(BIOS_INFO, "rs690_gfx_init step8.3.\n"); /* step 8.4 if the LTSSM could not see all 8 TS1 during Polling Active, it can still * time out and go back to Detect Idle.*/ set_pcie_enable_bits(dev, 0x02, 1 << 14, 1 << 14); - printk_info("rs690_gfx_init step8.4.\n"); + printk(BIOS_INFO, "rs690_gfx_init step8.4.\n"); /* step 8.5 shortens the enumeration timer */ set_pcie_enable_bits(dev, 0x70, 1 << 19, 1 << 19); - printk_info("rs690_gfx_init step8.5.\n"); + printk(BIOS_INFO, "rs690_gfx_init step8.5.\n"); /* step 8.6 blocks DMA traffic during C3 state */ set_pcie_enable_bits(dev, 0x10, 1 << 0, 0 << 0); - printk_info("rs690_gfx_init step8.6.\n"); + printk(BIOS_INFO, "rs690_gfx_init step8.6.\n"); /* step 8.7 Do not gate the electrical idle form the PHY * step 8.8 Enables the escape from L1L23 */ set_pcie_enable_bits(dev, 0xa0, 3 << 30, 3 << 30); - printk_info("rs690_gfx_init step8.8.\n"); + printk(BIOS_INFO, "rs690_gfx_init step8.8.\n"); /* step 8.9 Setting this register to 0x1 will workaround a PCI Compliance failure reported by Vista DTM. * SLOT_IMPLEMENTED@PCIE_CAP */ reg16 = pci_read_config16(dev, 0x5a); reg16 |= 0x100; pci_write_config16(dev, 0x5a, reg16); - printk_info("rs690_gfx_init step8.9.\n"); + printk(BIOS_INFO, "rs690_gfx_init step8.9.\n"); /* step 8.10 Setting this register to 0x1 will hide the Advanced Error Rporting Capabilities in the PCIE Brider. * This will workaround several failures reported by the PCI Compliance test under Vista DTM. */ set_nbmisc_enable_bits(nb_dev, 0x33, 1 << 31, 0 << 31); - printk_info("rs690_gfx_init step8.10.\n"); + printk(BIOS_INFO, "rs690_gfx_init step8.10.\n"); /* step 8.11 Sets REGS_DLP_IGNORE_IN_L1_EN to ignore DLLPs during L1 so that txclk can be turned off. */ set_pcie_enable_bits(nb_dev, 0x02, 1 << 0, 1 << 0); - printk_info("rs690_gfx_init step8.11.\n"); + printk(BIOS_INFO, "rs690_gfx_init step8.11.\n"); /* step 8.12 Sets REGS_LC_DONT_GO_TO_L0S_IF_L1_ARMED to prevent lc to go to from L0 to Rcv_L0s if L1 is armed. */ set_pcie_enable_bits(nb_dev, 0x02, 1 << 6, 1 << 6); - printk_info("rs690_gfx_init step8.12.\n"); + printk(BIOS_INFO, "rs690_gfx_init step8.12.\n"); /* step 8.13 Sets CMGOOD_OVERRIDE. */ set_nbmisc_enable_bits(nb_dev, 0x6a, 1 << 17, 1 << 17); - printk_info("rs690_gfx_init step8.13.\n"); + printk(BIOS_INFO, "rs690_gfx_init step8.13.\n"); /* step 9 Enable TLP Flushing, for non-AMD GFX devices and Hot-Plug devices only. */ /* skip */ @@ -619,7 +619,7 @@ void rs690_gfx_init(device_t nb_dev, device_t dev, u32 port) dual_port_configuration(nb_dev, dev); break; default: - printk_info("Incorrect configuration of external gfx slot.\n"); + printk(BIOS_INFO, "Incorrect configuration of external gfx slot.\n"); break; } } diff --git a/src/southbridge/amd/rs690/rs690_ht.c b/src/southbridge/amd/rs690/rs690_ht.c index ef4b34296e..26824b5322 100644 --- a/src/southbridge/amd/rs690/rs690_ht.c +++ b/src/southbridge/amd/rs690/rs690_ht.c @@ -53,7 +53,7 @@ static void pcie_init(struct device *dev) /* Enable pci error detecting */ u32 dword; - printk_info("pcie_init in rs690_ht.c\n"); + printk(BIOS_INFO, "pcie_init in rs690_ht.c\n"); /* System error enable */ dword = pci_read_config32(dev, 0x04); diff --git a/src/southbridge/amd/rs690/rs690_pcie.c b/src/southbridge/amd/rs690/rs690_pcie.c index 91e6bb1066..ad2e871db4 100644 --- a/src/southbridge/amd/rs690/rs690_pcie.c +++ b/src/southbridge/amd/rs690/rs690_pcie.c @@ -110,7 +110,7 @@ static void pcie_init(struct device *dev) /* Enable pci error detecting */ u32 dword; - printk_debug("pcie_init in rs690_pcie.c\n"); + printk(BIOS_DEBUG, "pcie_init in rs690_pcie.c\n"); /* System error enable */ dword = pci_read_config32(dev, 0x04); @@ -168,7 +168,7 @@ static void switching_gpp_configurations(device_t nb_dev, device_t sb_dev) *****************************************************************/ void enable_pcie_bar3(device_t nb_dev) { - printk_debug("enable_pcie_bar3()\n"); + printk(BIOS_DEBUG, "enable_pcie_bar3()\n"); set_nbcfg_enable_bits(nb_dev, 0x7C, 1 << 30, 1 << 30); /* Enables writes to the BAR3 register. */ set_nbcfg_enable_bits(nb_dev, 0x84, 7 << 16, 0 << 16); @@ -184,7 +184,7 @@ void enable_pcie_bar3(device_t nb_dev) *****************************************************************/ void disable_pcie_bar3(device_t nb_dev) { - printk_debug("disable_pcie_bar3()\n"); + printk(BIOS_DEBUG, "disable_pcie_bar3()\n"); set_nbcfg_enable_bits(nb_dev, 0x7C, 1 << 30, 0 << 30); /* Disable writes to the BAR3. */ pci_write_config32(nb_dev, 0x1C, 0); /* clear BAR3 address */ ProgK8TempMmioBase(0, EXT_CONF_BASE_ADDRESS, TEMP_MMIO_BASE_ADDRESS); @@ -206,7 +206,7 @@ void rs690_gpp_sb_init(device_t nb_dev, device_t dev, u32 port) device_t sb_dev; struct southbridge_amd_rs690_config *cfg = (struct southbridge_amd_rs690_config *)nb_dev->chip_info; - printk_debug("gpp_sb_init nb_dev=0x%p, dev=0x%p, port=0x%x\n", nb_dev, dev, port); + printk(BIOS_DEBUG, "gpp_sb_init nb_dev=0x%p, dev=0x%p, port=0x%x\n", nb_dev, dev, port); /* init GPP core */ set_pcie_enable_bits(nb_dev, 0x20 | PCIE_CORE_INDEX_GPPSB, 1 << 8, @@ -262,7 +262,7 @@ void rs690_gpp_sb_init(device_t nb_dev, device_t dev, u32 port) PcieReleasePortTraining(nb_dev, dev, port); if (!(AtiPcieCfg.Config & PCIE_GPP_COMPLIANCE)) { u8 res = PcieTrainPort(nb_dev, dev, port); - printk_debug("PcieTrainPort port=0x%x result=%d\n", port, res); + printk(BIOS_DEBUG, "PcieTrainPort port=0x%x result=%d\n", port, res); if (res) { AtiPcieCfg.PortDetect |= 1 << port; } diff --git a/src/southbridge/amd/rs780/rs780.c b/src/southbridge/amd/rs780/rs780.c index b7ec1154ce..471603f865 100644 --- a/src/southbridge/amd/rs780/rs780.c +++ b/src/southbridge/amd/rs780/rs780.c @@ -120,9 +120,9 @@ void rs780_nb_pci_table(device_t nb_dev) /* Program NB PCI table. */ temp16 = pci_read_config16(nb_dev, 0x04); - printk_debug("NB_PCI_REG04 = %x.\n", temp16); + printk(BIOS_DEBUG, "NB_PCI_REG04 = %x.\n", temp16); temp32 = pci_read_config32(nb_dev, 0x84); - printk_debug("NB_PCI_REG84 = %x.\n", temp32); + printk(BIOS_DEBUG, "NB_PCI_REG84 = %x.\n", temp32); pci_write_config8(nb_dev, 0x4c, 0x42); @@ -131,7 +131,7 @@ void rs780_nb_pci_table(device_t nb_dev) pci_write_config8(nb_dev, 0x4e, temp8); temp32 = pci_read_config32(nb_dev, 0x4c); - printk_debug("NB_PCI_REG4C = %x.\n", temp32); + printk(BIOS_DEBUG, "NB_PCI_REG4C = %x.\n", temp32); /* disable GFX debug. */ temp8 = pci_read_config8(nb_dev, 0x8d); @@ -250,7 +250,7 @@ void rs780_nb_gfx_dev_table(device_t nb_dev, device_t dev) /* Enable PCIe configuration space. */ set_htiu_enable_bits(nb_dev, 0x32, 0, 1<<28); - printk_info("GC is accessible from now on.\n"); + printk(BIOS_INFO, "GC is accessible from now on.\n"); } /*********************************************** @@ -272,7 +272,7 @@ void rs780_enable(device_t dev) device_t nb_dev = 0, sb_dev = 0; int dev_ind; - printk_info("rs780_enable: dev=%p, VID_DID=0x%x\n", dev, get_vid_did(dev)); + printk(BIOS_INFO, "rs780_enable: dev=%p, VID_DID=0x%x\n", dev, get_vid_did(dev)); nb_dev = dev_find_slot(0, PCI_DEVFN(0, 0)); if (!nb_dev) { @@ -290,7 +290,7 @@ void rs780_enable(device_t dev) dev_ind = dev->path.pci.devfn >> 3; switch (dev_ind) { case 0: /* bus0, dev0, fun0; */ - printk_info("Bus-0, Dev-0, Fun-0.\n"); + printk(BIOS_INFO, "Bus-0, Dev-0, Fun-0.\n"); enable_pcie_bar3(nb_dev); /* PCIEMiscInit */ config_gpp_core(nb_dev, sb_dev); rs780_gpp_sb_init(nb_dev, sb_dev, 8); @@ -304,12 +304,12 @@ void rs780_enable(device_t dev) break; case 1: /* bus0, dev1, APC. */ - printk_info("Bus-0, Dev-1, Fun-0.\n"); + printk(BIOS_INFO, "Bus-0, Dev-1, Fun-0.\n"); rs780_nb_gfx_dev_table(nb_dev, dev); break; case 2: /* bus0, dev2,3, two GFX */ case 3: - printk_info("Bus-0, Dev-2,3, Fun-0. enable=%d\n", dev->enabled); + printk(BIOS_INFO, "Bus-0, Dev-2,3, Fun-0. enable=%d\n", dev->enabled); set_nbmisc_enable_bits(nb_dev, 0x0c, 1 << dev_ind, (dev->enabled ? 0 : 1) << dev_ind); if (dev->enabled) @@ -319,7 +319,7 @@ void rs780_enable(device_t dev) case 5: case 6: case 7: - printk_info("Bus-0, Dev-4,5,6,7, Fun-0. enable=%d\n", + printk(BIOS_INFO, "Bus-0, Dev-4,5,6,7, Fun-0. enable=%d\n", dev->enabled); set_nbmisc_enable_bits(nb_dev, 0x0c, 1 << dev_ind, (dev->enabled ? 0 : 1) << dev_ind); @@ -327,7 +327,7 @@ void rs780_enable(device_t dev) rs780_gpp_sb_init(nb_dev, dev, dev_ind); break; case 8: /* bus0, dev8, SB */ - printk_info("Bus-0, Dev-8, Fun-0. enable=%d\n", dev->enabled); + printk(BIOS_INFO, "Bus-0, Dev-8, Fun-0. enable=%d\n", dev->enabled); set_nbmisc_enable_bits(nb_dev, 0x00, 1 << 6, (dev->enabled ? 1 : 0) << 6); if (dev->enabled) @@ -336,7 +336,7 @@ void rs780_enable(device_t dev) break; case 9: /* bus 0, dev 9,10, GPP */ case 10: - printk_info("Bus-0, Dev-9, 10, Fun-0. enable=%d\n", + printk(BIOS_INFO, "Bus-0, Dev-9, 10, Fun-0. enable=%d\n", dev->enabled); enable_pcie_bar3(nb_dev); /* PCIEMiscInit */ set_nbmisc_enable_bits(nb_dev, 0x0c, 1 << (7 + dev_ind), @@ -346,7 +346,7 @@ void rs780_enable(device_t dev) /* Dont call disable_pcie_bar3(nb_dev) here, otherwise the screen will crash. */ break; default: - printk_debug("unknown dev: %s\n", dev_path(dev)); + printk(BIOS_DEBUG, "unknown dev: %s\n", dev_path(dev)); } } diff --git a/src/southbridge/amd/rs780/rs780_cmn.c b/src/southbridge/amd/rs780/rs780_cmn.c index bf27794fc7..ab91074ad2 100644 --- a/src/southbridge/amd/rs780/rs780_cmn.c +++ b/src/southbridge/amd/rs780/rs780_cmn.c @@ -48,7 +48,7 @@ u32 pci_ext_read_config32(device_t nb_dev, device_t dev, u32 reg) { /*get BAR3 base address for nbcfg0x1c */ u32 addr = pci_read_config32(nb_dev, 0x1c) & ~0xF; - printk_debug("addr=%x,bus=%x,devfn=%x\n", addr, dev->bus->secondary, + printk(BIOS_DEBUG, "addr=%x,bus=%x,devfn=%x\n", addr, dev->bus->secondary, dev->path.pci.devfn); addr |= dev->bus->secondary << 20 | /* bus num */ dev->path.pci.devfn << 12 | reg; @@ -61,7 +61,7 @@ void pci_ext_write_config32(device_t nb_dev, device_t dev, u32 reg_pos, u32 mask /*get BAR3 base address for nbcfg0x1c */ u32 addr = pci_read_config32(nb_dev, 0x1c) & ~0xF; - /*printk_debug("write: addr=%x,bus=%x,devfn=%x\n", addr, dev->bus->secondary, + /*printk(BIOS_DEBUG, "write: addr=%x,bus=%x,devfn=%x\n", addr, dev->bus->secondary, dev->path.pci.devfn);*/ addr |= dev->bus->secondary << 20 | /* bus num */ dev->path.pci.devfn << 12 | reg_pos; @@ -271,7 +271,7 @@ u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port) mdelay(40); udelay(200); lc_state = nbpcie_p_read_index(dev, 0xa5); /* lc_state */ - printk_debug("PcieLinkTraining port=%x:lc current state=%x\n", + printk(BIOS_DEBUG, "PcieLinkTraining port=%x:lc current state=%x\n", port, lc_state); current = lc_state & 0x3f; /* get LC_CURRENT_STATE, bit0-5 */ @@ -297,7 +297,7 @@ u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port) reg |= lane_mask << 8 | lane_mask; reg = 0xE0E0; /* TODO: See the comments in rs780_pcie.c, at about line 145. */ nbpcie_ind_write_index(nb_dev, 0x65 | gfx_gpp_sb_sel, reg); - printk_debug("link_width=%x, lane_mask=%x", + printk(BIOS_DEBUG, "link_width=%x, lane_mask=%x", current_link_width, lane_mask); set_pcie_reset(); mdelay(1); @@ -311,7 +311,7 @@ u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port) reg = pci_ext_read_config32(nb_dev, dev, PCIE_VC0_RESOURCE_STATUS); - printk_debug("PcieTrainPort reg=0x%x\n", reg); + printk(BIOS_DEBUG, "PcieTrainPort reg=0x%x\n", reg); /* check bit1 */ if (reg & VC_NEGOTIATION_PENDING) { /* bit1=1 means the link needs to be re-trained. */ /* set bit8=1, bit0-2=bit4-6 */ diff --git a/src/southbridge/amd/rs780/rs780_early_setup.c b/src/southbridge/amd/rs780/rs780_early_setup.c index 5b9616f3ca..159d51f52e 100644 --- a/src/southbridge/amd/rs780/rs780_early_setup.c +++ b/src/southbridge/amd/rs780/rs780_early_setup.c @@ -147,25 +147,25 @@ static void get_cpu_rev() u32 eax; eax = cpuid_eax(1); - printk_info("get_cpu_rev EAX=0x%x.\n", eax); + printk(BIOS_INFO, "get_cpu_rev EAX=0x%x.\n", eax); if (eax <= 0xfff) - printk_info("CPU Rev is K8_Cx.\n"); + printk(BIOS_INFO, "CPU Rev is K8_Cx.\n"); else if (eax <= 0x10fff) - printk_info("CPU Rev is K8_Dx.\n"); + printk(BIOS_INFO, "CPU Rev is K8_Dx.\n"); else if (eax <= 0x20fff) - printk_info("CPU Rev is K8_Ex.\n"); + printk(BIOS_INFO, "CPU Rev is K8_Ex.\n"); else if (eax <= 0x40fff) - printk_info("CPU Rev is K8_Fx.\n"); + printk(BIOS_INFO, "CPU Rev is K8_Fx.\n"); else if (eax == 0x60fb1 || eax == 0x60f81) /*These two IDS are exception, they are G1. */ - printk_info("CPU Rev is K8_G1.\n"); + printk(BIOS_INFO, "CPU Rev is K8_G1.\n"); else if (eax <= 0X60FF0) - printk_info("CPU Rev is K8_G0.\n"); + printk(BIOS_INFO, "CPU Rev is K8_G0.\n"); else if (eax <= 0x100000) - printk_info("CPU Rev is K8_G1.\n"); + printk(BIOS_INFO, "CPU Rev is K8_G1.\n"); else if (eax <= 0x100f00) - printk_info("CPU Rev is Fam 10.\n"); + printk(BIOS_INFO, "CPU Rev is Fam 10.\n"); else - printk_info("CPU Rev is K8_10.\n"); + printk(BIOS_INFO, "CPU Rev is K8_10.\n"); } static u8 is_famly10() @@ -246,7 +246,7 @@ static void rs780_htinit() ************************/ reg = pci_read_config32(cpu_f0, 0x88); cpu_ht_freq = (reg & 0xf00) >> 8; - printk_info("rs780_htinit cpu_ht_freq=%x.\n", cpu_ht_freq); + printk(BIOS_INFO, "rs780_htinit cpu_ht_freq=%x.\n", cpu_ht_freq); rs780_f0 = PCI_DEV(0, 0, 0); //set_nbcfg_enable_bits(rs780_f0, 0xC8, 0x7<<24 | 0x7<<28, 1<<24 | 1<<28); @@ -260,7 +260,7 @@ static void rs780_htinit() * So we check 6 only, it would be faster. */ if ((cpu_ht_freq == 0x6) || (cpu_ht_freq == 0x5) || (cpu_ht_freq == 0x4) || (cpu_ht_freq == 0x2) || (cpu_ht_freq == 0x0)) { - printk_info("rs780_htinit: HT1 mode\n"); + printk(BIOS_INFO, "rs780_htinit: HT1 mode\n"); /* HT1 mode, RPR 8.4.2 */ /* set IBIAS code */ @@ -268,7 +268,7 @@ static void rs780_htinit() /* Optimizes chipset HT transmitter drive strength */ set_htiu_enable_bits(rs780_f0, 0x2A, 0x3, 0x1); } else if ((cpu_ht_freq > 0x6) && (cpu_ht_freq < 0xf)) { - printk_info("rs780_htinit: HT3 mode\n"); + printk(BIOS_INFO, "rs780_htinit: HT3 mode\n"); #if CONFIG_NORTHBRIDGE_AMD_AMDFAM10 == 1 /* save some spaces */ /* HT3 mode, RPR 8.4.3 */ @@ -330,7 +330,7 @@ static void k8_optimization() device_t k8_f0, k8_f2, k8_f3; msr_t msr; - printk_info("k8_optimization()\n"); + printk(BIOS_INFO, "k8_optimization()\n"); k8_f0 = PCI_DEV(0, 0x18, 0); k8_f2 = PCI_DEV(0, 0x18, 2); k8_f3 = PCI_DEV(0, 0x18, 3); @@ -373,7 +373,7 @@ void fam10_optimization() msr_t msr; u32 val; - printk_info("fam10_optimization()\n"); + printk(BIOS_INFO, "fam10_optimization()\n"); cpu_f0 = PCI_DEV(0, 0x18, 0); cpu_f2 = PCI_DEV(0, 0x18, 2); @@ -612,7 +612,7 @@ static void rs780_por_htiu_index_init(device_t nb_dev) *****************************************/ static void rs780_por_init(device_t nb_dev) { - printk_info("rs780_por_init\n"); + printk(BIOS_INFO, "rs780_por_init\n"); /* ATINB_PCICFG_POR_TABLE, initialize the values for rs780 PCI Config registers */ rs780_por_pcicfg_init(nb_dev); @@ -642,20 +642,20 @@ static void rs780_before_pci_init() static void rs780_early_setup() { device_t nb_dev = PCI_DEV(0, 0, 0); - printk_info("rs780_early_setup()\n"); + printk(BIOS_INFO, "rs780_early_setup()\n"); get_cpu_rev(); - /* The printk_info(s) below cause the system unstable. */ + /* The printk(BIOS_INFO, s) below cause the system unstable. */ switch (get_nb_rev(nb_dev)) { case REV_RS780_A11: - /* printk_info("NB Revision is A11.\n"); */ + /* printk(BIOS_INFO, "NB Revision is A11.\n"); */ break; case REV_RS780_A12: - /* printk_info("NB Revision is A12.\n"); */ + /* printk(BIOS_INFO, "NB Revision is A12.\n"); */ break; case REV_RS780_A13: - /* printk_info("NB Revision is A13.\n"); */ + /* printk(BIOS_INFO, "NB Revision is A13.\n"); */ break; } diff --git a/src/southbridge/amd/rs780/rs780_gfx.c b/src/southbridge/amd/rs780/rs780_gfx.c index aa46451410..808bcb175f 100644 --- a/src/southbridge/amd/rs780/rs780_gfx.c +++ b/src/southbridge/amd/rs780/rs780_gfx.c @@ -55,7 +55,7 @@ static u32 clkind_read(device_t dev, u32 index) static void clkind_write(device_t dev, u32 index, u32 data) { u32 gfx_bar2 = pci_read_config32(dev, 0x18) & ~0xF; - /* printk_info("gfx bar 2 %02x\n", gfx_bar2); */ + /* printk(BIOS_INFO, "gfx bar 2 %02x\n", gfx_bar2); */ *(u32*)(gfx_bar2+CLK_CNTL_INDEX) = index | 1<<7; *(u32*)(gfx_bar2+CLK_CNTL_DATA) = data; @@ -67,7 +67,7 @@ static void clkind_write(device_t dev, u32 index, u32 data) */ static void rs780_gfx_read_resources(device_t dev) { - printk_info("rs780_gfx_read_resources.\n"); + printk(BIOS_INFO, "rs780_gfx_read_resources.\n"); /* The initial value of 0x24 is 0xFFFFFFFF, which is confusing. Even if we write 0xFFFFFFFF into it, it will be 0xFFF00000, @@ -189,7 +189,7 @@ CIM_STATUS GetCreativeMMIO(MMIORANGE *pMMIO) { tempdev = dev_find_slot(Bus, Dev << 3); Value = pci_read_config32(tempdev, 0); - printk_debug("Dev ID %x \n", Value); + printk(BIOS_DEBUG, "Dev ID %x \n", Value); if((Value & 0xffff) == 0x1102) {//Creative //Found Creative SB @@ -220,7 +220,7 @@ CIM_STATUS GetCreativeMMIO(MMIORANGE *pMMIO) } } } - printk_debug(" MMIOStart %x MMIOLimit %x \n", MMIOStart, MMIOLimit); + printk(BIOS_DEBUG, " MMIOStart %x MMIOLimit %x \n", MMIOStart, MMIOLimit); if (MMIOStart < MMIOLimit) { Status = SetMMIO(MMIOStart>>8, MMIOLimit>>8, 0x80, pMMIO); @@ -310,7 +310,7 @@ static void internal_gfx_pci_dev_init(struct device *dev) deviceid = pci_read_config16(dev, PCI_DEVICE_ID); vendorid = pci_read_config16(dev, PCI_VENDOR_ID); - printk_info("internal_gfx_pci_dev_init device=%x, vendor=%x.\n", + printk(BIOS_INFO, "internal_gfx_pci_dev_init device=%x, vendor=%x.\n", deviceid, vendorid); command = pci_read_config16(dev, 0x04); @@ -420,7 +420,7 @@ static void internal_gfx_pci_dev_init(struct device *dev) vgainfo.ulBootUpEngineClock = 500 * 100; /* set boot up GFX engine clock. */ vgainfo.ulReserved1[0] = 0; vgainfo.ulReserved1[1] = 0; value = pci_read_config32(k8_f2, 0x94); - printk_debug("MEMCLK = %x\n", value&0x7); + printk(BIOS_DEBUG, "MEMCLK = %x\n", value&0x7); vgainfo.ulBootUpUMAClock = 333 * 100; /* set boot up UMA memory clock. */ vgainfo.ulBootUpSidePortClock = 0; /* disable SP. */ vgainfo.ulMinSidePortClock = 0; /* disable SP. */ @@ -447,14 +447,14 @@ static void internal_gfx_pci_dev_init(struct device *dev) vgainfo.usBootUpNBVoltage = 0x1a; value = pci_read_config32(nb_dev, 0xd0); - printk_debug("NB HT speed = %x.\n", value); + printk(BIOS_DEBUG, "NB HT speed = %x.\n", value); value = pci_read_config32(k8_f0, 0x88); - printk_debug("CPU HT speed = %x.\n", value); + printk(BIOS_DEBUG, "CPU HT speed = %x.\n", value); vgainfo.ulHTLinkFreq = 100 * 100; /* set HT speed. */ /* HT width. */ value = pci_read_config32(nb_dev, 0xc8); - printk_debug("HT width = %x.\n", value); + printk(BIOS_DEBUG, "HT width = %x.\n", value); vgainfo.usMinHTLinkWidth = 16; vgainfo.usMaxHTLinkWidth = 16; vgainfo.usUMASyncStartDelay = 322; @@ -585,10 +585,10 @@ static void rs780_internal_gfx_enable(device_t dev) u32 FB_Start, FB_End; #endif - printk_info("rs780_internal_gfx_enable dev = 0x%p, nb_dev = 0x%p.\n", dev, nb_dev); + printk(BIOS_INFO, "rs780_internal_gfx_enable dev = 0x%p, nb_dev = 0x%p.\n", dev, nb_dev); sysmem = rdmsr(0xc001001a); - printk_info("sysmem = %x_%x\n", sysmem.hi, sysmem.lo); + printk(BIOS_INFO, "sysmem = %x_%x\n", sysmem.hi, sysmem.lo); /* The system top memory in 780. */ pci_write_config32(nb_dev, 0x90, sysmem.lo); @@ -826,12 +826,12 @@ static void single_port_configuration(device_t nb_dev, device_t dev) struct southbridge_amd_rs780_config *cfg = (struct southbridge_amd_rs780_config *)nb_dev->chip_info; - printk_info("rs780_gfx_init single_port_configuration.\n"); + printk(BIOS_INFO, "rs780_gfx_init single_port_configuration.\n"); /* step 12 training, releases hold training for GFX port 0 (device 2) */ PcieReleasePortTraining(nb_dev, dev, 2); result = PcieTrainPort(nb_dev, dev, 2); - printk_info("rs780_gfx_init single_port_configuration step12.\n"); + printk(BIOS_INFO, "rs780_gfx_init single_port_configuration step12.\n"); /* step 13 Power Down Control */ /* step 13.1 Enables powering down transmitter and receiver pads along with PLL macros. */ @@ -851,7 +851,7 @@ static void single_port_configuration(device_t nb_dev, device_t dev) set_pcie_enable_bits(dev, 0xA2, 0xFF, 0x1); reg32 = nbpcie_p_read_index(dev, 0x29); width = reg32 & 0xFF; - printk_debug("GFX Inactive Lanes = 0x%x.\n", width); + printk(BIOS_DEBUG, "GFX Inactive Lanes = 0x%x.\n", width); switch (width) { case 1: case 2: @@ -868,11 +868,11 @@ static void single_port_configuration(device_t nb_dev, device_t dev) break; } } - printk_info("rs780_gfx_init single_port_configuration step13.\n"); + printk(BIOS_INFO, "rs780_gfx_init single_port_configuration step13.\n"); /* step 14 Reset Enumeration Timer, disables the shortening of the enumeration timer */ set_pcie_enable_bits(dev, 0x70, 1 << 19, 1 << 19); - printk_info("rs780_gfx_init single_port_configuration step14.\n"); + printk(BIOS_INFO, "rs780_gfx_init single_port_configuration step14.\n"); } static void dual_port_configuration(device_t nb_dev, device_t dev) @@ -905,7 +905,7 @@ static void dual_port_configuration(device_t nb_dev, device_t dev) } else { /* step 16.b Link Training was successful */ reg32 = nbpcie_p_read_index(dev, 0xa2); width = (reg32 >> 4) & 0x7; - printk_debug("GFX LC_LINK_WIDTH = 0x%x.\n", width); + printk(BIOS_DEBUG, "GFX LC_LINK_WIDTH = 0x%x.\n", width); switch (width) { case 1: case 2: @@ -983,7 +983,7 @@ void rs780_gfx_init(device_t nb_dev, device_t dev, u32 port) struct southbridge_amd_rs780_config *cfg = (struct southbridge_amd_rs780_config *)nb_dev->chip_info; - printk_info("rs780_gfx_init, nb_dev=0x%p, dev=0x%p, port=0x%x.\n", + printk(BIOS_INFO, "rs780_gfx_init, nb_dev=0x%p, dev=0x%p, port=0x%x.\n", nb_dev, dev, port); /* GFX Core Initialization */ @@ -995,13 +995,13 @@ void rs780_gfx_init(device_t nb_dev, device_t dev, u32 port) if (cfg->gfx_dual_slot) set_nbmisc_enable_bits(nb_dev, 0x33, 1 << 3, 1 << 3); } - printk_info("rs780_gfx_init step1.\n"); + printk(BIOS_INFO, "rs780_gfx_init step1.\n"); /* step 1.1, dual-slot gfx configuration (only need if CMOS option is enabled) */ /* AMD calls the configuration CrossFire */ if (cfg->gfx_dual_slot) set_nbmisc_enable_bits(nb_dev, 0x0, 0xf << 8, 5 << 8); - printk_info("rs780_gfx_init step2.\n"); + printk(BIOS_INFO, "rs780_gfx_init step2.\n"); /* step 2, TMDS, (only need if CMOS option is enabled) */ if (cfg->gfx_tmds) { @@ -1020,7 +1020,7 @@ void rs780_gfx_init(device_t nb_dev, device_t dev, u32 port) set_nbmisc_enable_bits(nb_dev, 0x28, 3 << 6 | 3 << 8 | 3 << 10, 1 << 6 | 1 << 8 | 1 << 10); reg32 = nbmisc_read_index(nb_dev, 0x28); - printk_info("misc 28 = %x\n", reg32); + printk(BIOS_INFO, "misc 28 = %x\n", reg32); /* 5.9.1.6.Selects the single ended GFX REFCLK to be the source for core logic. */ set_nbmisc_enable_bits(nb_dev, 0x6C, 1 << 31, 1 << 31); @@ -1038,7 +1038,7 @@ void rs780_gfx_init(device_t nb_dev, device_t dev, u32 port) set_nbmisc_enable_bits(nb_dev, 0x28, 3 << 6 | 3 << 8 | 3 << 10, 0); reg32 = nbmisc_read_index(nb_dev, 0x28); - printk_info("misc 28 = %x\n", reg32); + printk(BIOS_INFO, "misc 28 = %x\n", reg32); /* 5.9.1.6.Selects the single ended GFX REFCLK to be the source for core logic. */ set_nbmisc_enable_bits(nb_dev, 0x6C, 1 << 31, 0 << 31); @@ -1079,7 +1079,7 @@ void rs780_gfx_init(device_t nb_dev, device_t dev, u32 port) /* release hold training for device 2. GFX initialization is done. */ set_nbmisc_enable_bits(nb_dev, 0x8, 1 << 4, 0 << 4); dynamic_link_width_control(nb_dev, dev, cfg->gfx_link_width); - printk_info("rs780_gfx_init step7.\n"); + printk(BIOS_INFO, "rs780_gfx_init step7.\n"); return; } @@ -1087,11 +1087,11 @@ void rs780_gfx_init(device_t nb_dev, device_t dev, u32 port) /* 5.9.12.1 sets RCB timeout to be 25ms */ /* 5.9.12.2. RCB Cpl timeout on link down. */ set_pcie_enable_bits(dev, 0x70, 7 << 16 | 1 << 19, 4 << 16 | 1 << 19); - printk_info("rs780_gfx_init step5.9.12.1.\n"); + printk(BIOS_INFO, "rs780_gfx_init step5.9.12.1.\n"); /* step 5.9.12.3 disables slave ordering logic */ set_pcie_enable_bits(nb_dev, 0x20, 1 << 8, 1 << 8); - printk_info("rs780_gfx_init step5.9.12.3.\n"); + printk(BIOS_INFO, "rs780_gfx_init step5.9.12.3.\n"); /* step 5.9.12.4 sets DMA payload size to 64 bytes */ set_pcie_enable_bits(nb_dev, 0x10, 7 << 10, 4 << 10); @@ -1113,7 +1113,7 @@ void rs780_gfx_init(device_t nb_dev, device_t dev, u32 port) /* 5.9.12.9 CMGOOD_OVERRIDE for end point initiated lane degradation. */ set_nbmisc_enable_bits(nb_dev, 0x6a, 1 << 17, 1 << 17); - printk_info("rs780_gfx_init step5.9.12.9.\n"); + printk(BIOS_INFO, "rs780_gfx_init step5.9.12.9.\n"); /* 5.9.12.10 Sets the timer in Config state from 20us to */ /* 5.9.12.11 De-asserts RX_EN in L0s. */ @@ -1188,7 +1188,7 @@ void rs780_gfx_init(device_t nb_dev, device_t dev, u32 port) dual_port_configuration(nb_dev, dev); break; default: - printk_info("Incorrect configuration of external gfx slot.\n"); + printk(BIOS_INFO, "Incorrect configuration of external gfx slot.\n"); break; } } diff --git a/src/southbridge/amd/rs780/rs780_ht.c b/src/southbridge/amd/rs780/rs780_ht.c index b3fa05a529..03d4f84645 100644 --- a/src/southbridge/amd/rs780/rs780_ht.c +++ b/src/southbridge/amd/rs780/rs780_ht.c @@ -53,7 +53,7 @@ static void pcie_init(struct device *dev) /* Enable pci error detecting */ u32 dword; - printk_info("pcie_init in rs780_ht.c\n"); + printk(BIOS_INFO, "pcie_init in rs780_ht.c\n"); /* System error enable */ dword = pci_read_config32(dev, 0x04); diff --git a/src/southbridge/amd/rs780/rs780_pcie.c b/src/southbridge/amd/rs780/rs780_pcie.c index b778af3aa6..186266b8f1 100644 --- a/src/southbridge/amd/rs780/rs780_pcie.c +++ b/src/southbridge/amd/rs780/rs780_pcie.c @@ -106,7 +106,7 @@ static void pcie_init(struct device *dev) /* Enable pci error detecting */ u32 dword; - printk_debug("pcie_init in rs780_pcie.c\n"); + printk(BIOS_DEBUG, "pcie_init in rs780_pcie.c\n"); /* System error enable */ dword = pci_read_config32(dev, 0x04); @@ -216,7 +216,7 @@ static void switching_gpp_configurations(device_t nb_dev, device_t sb_dev) *****************************************************************/ void enable_pcie_bar3(device_t nb_dev) { - printk_debug("enable_pcie_bar3()\n"); + printk(BIOS_DEBUG, "enable_pcie_bar3()\n"); set_nbcfg_enable_bits(nb_dev, 0x7C, 1 << 30, 1 << 30); /* Enables writes to the BAR3 register. */ set_nbcfg_enable_bits(nb_dev, 0x84, 7 << 16, 0 << 16); @@ -232,7 +232,7 @@ void enable_pcie_bar3(device_t nb_dev) *****************************************************************/ void disable_pcie_bar3(device_t nb_dev) { - printk_debug("disable_pcie_bar3()\n"); + printk(BIOS_DEBUG, "disable_pcie_bar3()\n"); pci_write_config32(nb_dev, 0x1C, 0); /* clear BAR3 address */ set_nbcfg_enable_bits(nb_dev, 0x7C, 1 << 30, 0 << 30); /* Disable writes to the BAR3. */ ProgK8TempMmioBase(0, EXT_CONF_BASE_ADDRESS, TEMP_MMIO_BASE_ADDRESS); @@ -255,7 +255,7 @@ void rs780_gpp_sb_init(device_t nb_dev, device_t dev, u32 port) u32 gfx_gpp_sb_sel; struct southbridge_amd_rs780_config *cfg = (struct southbridge_amd_rs780_config *)nb_dev->chip_info; - printk_debug("gpp_sb_init nb_dev=0x%p, dev=0x%p, port=0x%p\n", nb_dev, dev, port); + printk(BIOS_DEBUG, "gpp_sb_init nb_dev=0x%p, dev=0x%p, port=0x%p\n", nb_dev, dev, port); gfx_gpp_sb_sel = port >= 4 && port <= 8 ? PCIE_CORE_INDEX_GPPSB : /* 4,5,6,7,8 */ @@ -369,7 +369,7 @@ void rs780_gpp_sb_init(device_t nb_dev, device_t dev, u32 port) PcieReleasePortTraining(nb_dev, dev, port); if (!(AtiPcieCfg.Config & PCIE_GPP_COMPLIANCE)) { u8 res = PcieTrainPort(nb_dev, dev, port); - printk_debug("PcieTrainPort port=0x%x result=%d\n", port, res); + printk(BIOS_DEBUG, "PcieTrainPort port=0x%x result=%d\n", port, res); if (res) { AtiPcieCfg.PortDetect |= 1 << port; } diff --git a/src/southbridge/amd/sb600/sb600.c b/src/southbridge/amd/sb600/sb600.c index 1e34786b77..d9b3dcc9e4 100644 --- a/src/southbridge/amd/sb600/sb600.c +++ b/src/southbridge/amd/sb600/sb600.c @@ -118,7 +118,7 @@ void sb600_enable(device_t dev) u32 devfn; - printk_debug("sb600_enable()\n"); + printk(BIOS_DEBUG, "sb600_enable()\n"); /* * 0:12.0 SATA bit 8 of sm_dev 0xac : 1 - enable, default + 32 * 3 @@ -220,7 +220,7 @@ void sb600_enable(device_t dev) index += 32 * 4; break; default: - printk_debug("unknown dev: %s deviceid=%4x\n", dev_path(dev), + printk(BIOS_DEBUG, "unknown dev: %s deviceid=%4x\n", dev_path(dev), deviceid); } } diff --git a/src/southbridge/amd/sb600/sb600_early_setup.c b/src/southbridge/amd/sb600/sb600_early_setup.c index 29c215adba..b7581ec352 100644 --- a/src/southbridge/amd/sb600/sb600_early_setup.c +++ b/src/southbridge/amd/sb600/sb600_early_setup.c @@ -284,16 +284,16 @@ static void sb600_devices_por_init(void) device_t dev; u8 byte; - printk_info("sb600_devices_por_init()\n"); + printk(BIOS_INFO, "sb600_devices_por_init()\n"); /* SMBus Device, BDF:0-20-0 */ - printk_info("sb600_devices_por_init(): SMBus Device, BDF:0-20-0\n"); + printk(BIOS_INFO, "sb600_devices_por_init(): SMBus Device, BDF:0-20-0\n"); dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0); if (dev == PCI_DEV_INVALID) { die("SMBUS controller not found\r\n"); /* NOT REACHED */ } - printk_info("SMBus controller enabled, sb revision is 0x%x\r\n", + printk(BIOS_INFO, "SMBus controller enabled, sb revision is 0x%x\r\n", get_sb600_revision()); /* sbPorAtStartOfTblCfg */ @@ -372,7 +372,7 @@ static void sb600_devices_por_init(void) outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); /* IDE Device, BDF:0-20-1 */ - printk_info("sb600_devices_por_init(): IDE Device, BDF:0-20-1\n"); + printk(BIOS_INFO, "sb600_devices_por_init(): IDE Device, BDF:0-20-1\n"); dev = pci_locate_device(PCI_ID(0x1002, 0x438C), 0); /* Disable prefetch */ byte = pci_read_config8(dev, 0x63); @@ -380,7 +380,7 @@ static void sb600_devices_por_init(void) pci_write_config8(dev, 0x63, byte); /* LPC Device, BDF:0-20-3 */ - printk_info("sb600_devices_por_init(): LPC Device, BDF:0-20-3\n"); + printk(BIOS_INFO, "sb600_devices_por_init(): LPC Device, BDF:0-20-3\n"); dev = pci_locate_device(PCI_ID(0x1002, 0x438D), 0); /* DMA enable */ pci_write_config8(dev, 0x40, 0x04); @@ -417,7 +417,7 @@ static void sb600_devices_por_init(void) /* P2P Bridge, BDF:0-20-4, the configuration of the registers in this dev are copied from CIM, * TODO: I don't know what are their mean? */ - printk_info("sb600_devices_por_init(): P2P Bridge, BDF:0-20-4\n"); + printk(BIOS_INFO, "sb600_devices_por_init(): P2P Bridge, BDF:0-20-4\n"); dev = pci_locate_device(PCI_ID(0x1002, 0x4384), 0); /* I don't know why CIM tried to write into a read-only reg! */ /*pci_write_config8(dev, 0x0c, 0x20) */ ; @@ -448,7 +448,7 @@ static void sb600_devices_por_init(void) pci_write_config8(dev, 0x50, 0x01); /* SATA Device, BDF:0-18-0, Non-Raid-5 SATA controller */ - printk_info("sb600_devices_por_init(): SATA Device, BDF:0-18-0\n"); + printk(BIOS_INFO, "sb600_devices_por_init(): SATA Device, BDF:0-18-0\n"); dev = pci_locate_device(PCI_ID(0x1002, 0x4380), 0); /*PHY Global Control, we are using A14. @@ -479,7 +479,7 @@ static void sb600_pmio_por_init(void) { u8 byte; - printk_info("sb600_pmio_por_init()\n"); + printk(BIOS_INFO, "sb600_pmio_por_init()\n"); /* K8KbRstEn, KB_RST# control for K8 system. */ byte = pmio_read(0x66); byte |= 0x20; @@ -676,7 +676,7 @@ static void sb600_before_pci_init(void) */ static void sb600_early_setup(void) { - printk_info("sb600_early_setup()\n"); + printk(BIOS_INFO, "sb600_early_setup()\n"); sb600_por_init(); } diff --git a/src/southbridge/amd/sb600/sb600_hda.c b/src/southbridge/amd/sb600/sb600_hda.c index 95e3744db5..3ba1fe910e 100644 --- a/src/southbridge/amd/sb600/sb600_hda.c +++ b/src/southbridge/amd/sb600/sb600_hda.c @@ -86,7 +86,7 @@ no_codec: /* Codec Not found */ /* Put HDA back in reset (BAR + 0x8) [0] */ set_bits(base + 0x08, 1, 0); - printk_debug("No codec!\n"); + printk(BIOS_DEBUG, "No codec!\n"); return 0; } @@ -156,9 +156,9 @@ static u32 find_verb(u32 viddid, u32 ** verb) device_t azalia_dev = dev_find_slot(0, PCI_DEVFN(0x14, 2)); struct southbridge_amd_sb600_config *cfg = (struct southbridge_amd_sb600_config *)azalia_dev->chip_info; - printk_debug("Dev=%s\n", dev_path(azalia_dev)); - printk_debug("Default viddid=%x\n", cfg->hda_viddid); - printk_debug("Reading viddid=%x\n", viddid); + printk(BIOS_DEBUG, "Dev=%s\n", dev_path(azalia_dev)); + printk(BIOS_DEBUG, "Default viddid=%x\n", cfg->hda_viddid); + printk(BIOS_DEBUG, "Reading viddid=%x\n", viddid); if (!cfg) return 0; if (viddid != cfg->hda_viddid) @@ -232,15 +232,15 @@ static void codec_init(u32 base, int addr) dword = read32(base + 0x64); /* 2 */ - printk_debug("codec viddid: %08x\n", dword); + printk(BIOS_DEBUG, "codec viddid: %08x\n", dword); verb_size = find_verb(dword, &verb); if (!verb_size) { - printk_debug("No verb!\n"); + printk(BIOS_DEBUG, "No verb!\n"); return; } - printk_debug("verb_size: %d\n", verb_size); + printk(BIOS_DEBUG, "verb_size: %d\n", verb_size); /* 3 */ for (i = 0; i < verb_size; i++) { if (wait_for_ready(base) == -1) @@ -251,7 +251,7 @@ static void codec_init(u32 base, int addr) if (wait_for_valid(base) == -1) return; } - printk_debug("verb loaded!\n"); + printk(BIOS_DEBUG, "verb loaded!\n"); } static void codecs_init(u32 base, u32 codec_mask) @@ -302,11 +302,11 @@ static void hda_init(struct device *dev) return; base = ((u32)res->base); - printk_debug("base = 0x%x\n", base); + printk(BIOS_DEBUG, "base = 0x%x\n", base); codec_mask = codec_detect(base); if (codec_mask) { - printk_debug("codec_mask = %02x\n", codec_mask); + printk(BIOS_DEBUG, "codec_mask = %02x\n", codec_mask); codecs_init(base, codec_mask); } } diff --git a/src/southbridge/amd/sb600/sb600_lpc.c b/src/southbridge/amd/sb600/sb600_lpc.c index a79cef9cf4..1f3253f55b 100644 --- a/src/southbridge/amd/sb600/sb600_lpc.c +++ b/src/southbridge/amd/sb600/sb600_lpc.c @@ -130,8 +130,7 @@ static void sb600_lpc_enable_childrens_resources(device_t dev) continue; base = res->base; end = resource_end(res); - printk_debug - ("sb600 lpc decode:%s, base=0x%08x, end=0x%08x\n", + printk(BIOS_DEBUG, "sb600 lpc decode:%s, base=0x%08x, end=0x%08x\n", dev_path(child), base, end); switch (base) { case 0x60: /* KB */ diff --git a/src/southbridge/amd/sb600/sb600_sata.c b/src/southbridge/amd/sb600/sb600_sata.c index 251f5ad2f0..0feebac92f 100644 --- a/src/southbridge/amd/sb600/sb600_sata.c +++ b/src/southbridge/amd/sb600/sb600_sata.c @@ -35,22 +35,22 @@ static int sata_drive_detect(int portnum, u16 iobar) while (byte = inb(iobar + 0x6), byte2 = inb(iobar + 0x7), (byte != (0xA0 + 0x10 * (portnum % 2))) || ((byte2 & 0x88) != 0)) { - printk_spew("0x6=%x, 0x7=%x\n", byte, byte2); + printk(BIOS_SPEW, "0x6=%x, 0x7=%x\n", byte, byte2); if (byte != (0xA0 + 0x10 * (portnum % 2))) { /* This will happen at the first iteration of this loop * if the first SATA port is unpopulated and the * second SATA port is poulated. */ - printk_debug("drive no longer selected after %i ms, " + printk(BIOS_DEBUG, "drive no longer selected after %i ms, " "retrying init\n", i * 10); return 1; } else - printk_spew("drive detection not yet completed, " + printk(BIOS_SPEW, "drive detection not yet completed, " "waiting...\n"); mdelay(10); i++; } - printk_spew("drive detection done after %i ms\n", i * 10); + printk(BIOS_SPEW, "drive detection done after %i ms\n", i * 10); return 0; } @@ -91,12 +91,12 @@ static void sata_init(struct device *dev) sata_bar3 = pci_read_config16(dev, 0x1C) & ~0x3; sata_bar4 = pci_read_config16(dev, 0x20) & ~0xf; - printk_spew("sata_bar0=%x\n", sata_bar0); /* 3030 */ - printk_spew("sata_bar1=%x\n", sata_bar1); /* 3070 */ - printk_spew("sata_bar2=%x\n", sata_bar2); /* 3040 */ - printk_spew("sata_bar3=%x\n", sata_bar3); /* 3080 */ - printk_spew("sata_bar4=%x\n", sata_bar4); /* 3000 */ - printk_spew("sata_bar5=%x\n", sata_bar5); /* e0309000 */ + printk(BIOS_SPEW, "sata_bar0=%x\n", sata_bar0); /* 3030 */ + printk(BIOS_SPEW, "sata_bar1=%x\n", sata_bar1); /* 3070 */ + printk(BIOS_SPEW, "sata_bar2=%x\n", sata_bar2); /* 3040 */ + printk(BIOS_SPEW, "sata_bar3=%x\n", sata_bar3); /* 3080 */ + printk(BIOS_SPEW, "sata_bar4=%x\n", sata_bar4); /* 3000 */ + printk(BIOS_SPEW, "sata_bar5=%x\n", sata_bar5); /* e0309000 */ /* Program the 2C to 0x43801002 */ dword = 0x43801002; @@ -173,13 +173,13 @@ static void sata_init(struct device *dev) for (i = 0; i < 4; i++) { byte = read8(sata_bar5 + 0x128 + 0x80 * i); - printk_spew("SATA port %i status = %x\n", i, byte); + printk(BIOS_SPEW, "SATA port %i status = %x\n", i, byte); byte &= 0xF; if( byte == 0x1 ) { /* If the drive status is 0x1 then we see it but we aren't talking to it. */ /* Try to do something about it. */ - printk_spew("SATA device detected but not talking. Trying lower speed.\n"); + printk(BIOS_SPEW, "SATA device detected but not talking. Trying lower speed.\n"); /* Read in Port-N Serial ATA Control Register */ byte = read8(sata_bar5 + 0x12C + 0x80 * i); @@ -200,7 +200,7 @@ static void sata_init(struct device *dev) /* Reread status */ byte = read8(sata_bar5 + 0x128 + 0x80 * i); - printk_spew("SATA port %i status = %x\n", i, byte); + printk(BIOS_SPEW, "SATA port %i status = %x\n", i, byte); byte &= 0xF; } @@ -209,13 +209,13 @@ static void sata_init(struct device *dev) if (!sata_drive_detect(i, ((i / 2) == 0) ? sata_bar0 : sata_bar2)) break; } - printk_debug("%s %s device is %sready after %i tries\n", + printk(BIOS_DEBUG, "%s %s device is %sready after %i tries\n", (i / 2) ? "Secondary" : "Primary", (i % 2 ) ? "Slave" : "Master", (j == 10) ? "not " : "", (j == 10) ? j : j + 1); } else { - printk_debug("No %s %s SATA drive on Slot%i\n", + printk(BIOS_DEBUG, "No %s %s SATA drive on Slot%i\n", (i / 2) ? "Secondary" : "Primary", (i % 2 ) ? "Slave" : "Master", i); } @@ -240,7 +240,7 @@ static void sata_init(struct device *dev) /* word = pm_ioread(0x28); */ /* byte = pm_ioread(0x29); */ /* word |= byte<<8; */ - /* printk_debug("AcpiGpe0Blk addr = %x\n", word); */ + /* printk(BIOS_DEBUG, "AcpiGpe0Blk addr = %x\n", word); */ /* write32(word, 0x80000000); */ } diff --git a/src/southbridge/amd/sb600/sb600_sm.c b/src/southbridge/amd/sb600/sb600_sm.c index 8e275291ba..6a18bfeea5 100644 --- a/src/southbridge/amd/sb600/sb600_sm.c +++ b/src/southbridge/amd/sb600/sb600_sm.c @@ -54,7 +54,7 @@ static void sm_init(device_t dev) u32 on; u32 nmi_option; - printk_info("sm_init().\n"); + printk(BIOS_INFO, "sm_init().\n"); ioapic_base = pci_read_config32(dev, 0x74) & (0xffffffe0); /* some like mem resource, but does not have enable bit */ /* Don't rename APIC ID */ @@ -98,7 +98,7 @@ static void sm_init(device_t dev) } byte |= 1 << 2; pm_iowrite(0x74, byte); - printk_info("set power %s after power fail\n", on ? "on" : "off"); + printk(BIOS_INFO, "set power %s after power fail\n", on ? "on" : "off"); /* sb600 rpr:2.3.3: */ byte = pm_ioread(0x9A); @@ -154,10 +154,10 @@ static void sm_init(device_t dev) get_option(&nmi_option, "nmi"); if (nmi_option) { byte &= ~(1 << 7); /* set NMI */ - printk_info("++++++++++set NMI+++++\n"); + printk(BIOS_INFO, "++++++++++set NMI+++++\n"); } else { byte |= (1 << 7); /* Can not mask NMI from PCI-E and NMI_NOW */ - printk_info("++++++++++no set NMI+++++\n"); + printk(BIOS_INFO, "++++++++++no set NMI+++++\n"); } byte &= ~(1 << 7); if (byte != byte_old) { @@ -197,9 +197,9 @@ static void sm_init(device_t dev) /* 3.12: Enabling AB and BIF Clock Gating */ abcfg_reg(0x10054, 0xFFFF0000, 0x1040000); abcfg_reg(0x54, 0xFF << 16, 4 << 16); - printk_info("3.11, ABCFG:0x54\n"); + printk(BIOS_INFO, "3.11, ABCFG:0x54\n"); abcfg_reg(0x54, 1 << 24, 1 << 24); - printk_info("3.12, ABCFG:0x54\n"); + printk(BIOS_INFO, "3.12, ABCFG:0x54\n"); abcfg_reg(0x98, 0x0000FF00, 0x00004700); /* 3.13:Enabling AB Int_Arbiter Enhancement (for All Revisions) */ @@ -211,7 +211,7 @@ static void sm_init(device_t dev) abcfg_reg(0x10098, 0xFFFFFFFF, 0x4000); abcfg_reg(0x04, 0xFFFFFFFF, 0x6); - printk_info("sm_init() end\n"); + printk(BIOS_INFO, "sm_init() end\n"); /* Enable NbSb virtual channel */ axcfg_reg(0x114, 0x3f << 1, 0 << 1); diff --git a/src/southbridge/amd/sb600/sb600_smbus.c b/src/southbridge/amd/sb600/sb600_smbus.c index df7ec56c3e..9e14930b09 100644 --- a/src/southbridge/amd/sb600/sb600_smbus.c +++ b/src/southbridge/amd/sb600/sb600_smbus.c @@ -188,7 +188,7 @@ static void alink_ab_indx(u32 reg_space, u32 reg_addr, tmp &= ~mask; tmp |= val; - /* printk_debug("about write %x, index=%x", tmp, (reg_space&0x3)<<30 | reg_addr); */ + /* printk(BIOS_DEBUG, "about write %x, index=%x", tmp, (reg_space&0x3)<<30 | reg_addr); */ outl((reg_space & 0x3) << 30 | reg_addr, AB_INDX); /* probably we dont have to do it again. */ outl(tmp, AB_DATA); } diff --git a/src/southbridge/amd/sb600/sb600_usb.c b/src/southbridge/amd/sb600/sb600_usb.c index 134e12560e..b6e1fbec6b 100644 --- a/src/southbridge/amd/sb600/sb600_usb.c +++ b/src/southbridge/amd/sb600/sb600_usb.c @@ -94,7 +94,7 @@ static void usb_init2(struct device *dev) /* pci_write_config32(dev, 0xf8, dword); */ usb2_bar0 = pci_read_config32(dev, 0x10) & ~0xFF; - printk_info("usb2_bar0=0x%x\n", usb2_bar0); + printk(BIOS_INFO, "usb2_bar0=0x%x\n", usb2_bar0); /* RPR5.4 Enables the USB PHY auto calibration resister to match 45ohm resistence */ dword = 0x00020F00; diff --git a/src/southbridge/amd/sb700/sb700.c b/src/southbridge/amd/sb700/sb700.c index 4bbde6dba2..39ae3a6b34 100644 --- a/src/southbridge/amd/sb700/sb700.c +++ b/src/southbridge/amd/sb700/sb700.c @@ -118,7 +118,7 @@ void sb700_enable(device_t dev) u32 devfn; - printk_debug("sb700_enable()\n"); + printk(BIOS_DEBUG, "sb700_enable()\n"); /* * 0:11.0 SATA bit 8 of sm_dev 0xac : 1 - enable, default + 32 * 3 @@ -221,7 +221,7 @@ void sb700_enable(device_t dev) index = 4; break; default: - printk_debug("unknown dev: %s deviceid=%4x\n", dev_path(dev), + printk(BIOS_DEBUG, "unknown dev: %s deviceid=%4x\n", dev_path(dev), deviceid); } } diff --git a/src/southbridge/amd/sb700/sb700_early_setup.c b/src/southbridge/amd/sb700/sb700_early_setup.c index a063c70cf9..3777bd6288 100644 --- a/src/southbridge/amd/sb700/sb700_early_setup.c +++ b/src/southbridge/amd/sb700/sb700_early_setup.c @@ -300,16 +300,16 @@ static void sb700_devices_por_init(void) device_t dev; u8 byte; - printk_info("sb700_devices_por_init()\n"); + printk(BIOS_INFO, "sb700_devices_por_init()\n"); /* SMBus Device, BDF:0-20-0 */ - printk_info("sb700_devices_por_init(): SMBus Device, BDF:0-20-0\n"); + printk(BIOS_INFO, "sb700_devices_por_init(): SMBus Device, BDF:0-20-0\n"); dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0); if (dev == PCI_DEV_INVALID) { die("SMBUS controller not found\r\n"); /* NOT REACHED */ } - printk_info("SMBus controller enabled, sb revision is A%x\r\n", + printk(BIOS_INFO, "SMBus controller enabled, sb revision is A%x\r\n", set_sb700_revision()); /* sbPorAtStartOfTblCfg */ @@ -378,7 +378,7 @@ static void sb700_devices_por_init(void) outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); /* IDE Device, BDF:0-20-1 */ - printk_info("sb700_devices_por_init(): IDE Device, BDF:0-20-1\n"); + printk(BIOS_INFO, "sb700_devices_por_init(): IDE Device, BDF:0-20-1\n"); dev = pci_locate_device(PCI_ID(0x1002, 0x439C), 0); /* Disable prefetch */ byte = pci_read_config8(dev, 0x63); @@ -386,7 +386,7 @@ static void sb700_devices_por_init(void) pci_write_config8(dev, 0x63, byte); /* LPC Device, BDF:0-20-3 */ - printk_info("sb700_devices_por_init(): LPC Device, BDF:0-20-3\n"); + printk(BIOS_INFO, "sb700_devices_por_init(): LPC Device, BDF:0-20-3\n"); dev = pci_locate_device(PCI_ID(0x1002, 0x439D), 0); /* DMA enable */ pci_write_config8(dev, 0x40, 0x04); @@ -423,7 +423,7 @@ static void sb700_devices_por_init(void) /* P2P Bridge, BDF:0-20-4, the configuration of the registers in this dev are copied from CIM, */ - printk_info("sb700_devices_por_init(): P2P Bridge, BDF:0-20-4\n"); + printk(BIOS_INFO, "sb700_devices_por_init(): P2P Bridge, BDF:0-20-4\n"); dev = pci_locate_device(PCI_ID(0x1002, 0x4384), 0); /* Arbiter enable. */ @@ -440,7 +440,7 @@ static void sb700_devices_por_init(void) pci_write_config8(dev, 0x50, 0x01); /* SATA Device, BDF:0-17-0, Non-Raid-5 SATA controller */ - printk_info("sb700_devices_por_init(): SATA Device, BDF:0-18-0\n"); + printk(BIOS_INFO, "sb700_devices_por_init(): SATA Device, BDF:0-18-0\n"); dev = pci_locate_device(PCI_ID(0x1002, 0x4390), 0); /*PHY Global Control*/ @@ -457,7 +457,7 @@ static void sb700_pmio_por_init(void) { u8 byte; - printk_info("sb700_pmio_por_init()\n"); + printk(BIOS_INFO, "sb700_pmio_por_init()\n"); /* K8KbRstEn, KB_RST# control for K8 system. */ byte = pmio_read(0x66); byte |= 0x20; @@ -602,7 +602,7 @@ static void sb700_before_pci_init(void) */ static void sb700_early_setup(void) { - printk_info("sb700_early_setup()\n"); + printk(BIOS_INFO, "sb700_early_setup()\n"); sb700_por_init(); } diff --git a/src/southbridge/amd/sb700/sb700_hda.c b/src/southbridge/amd/sb700/sb700_hda.c index 2f55c944c7..af1361692a 100644 --- a/src/southbridge/amd/sb700/sb700_hda.c +++ b/src/southbridge/amd/sb700/sb700_hda.c @@ -86,7 +86,7 @@ no_codec: /* Codec Not found */ /* Put HDA back in reset (BAR + 0x8) [0] */ set_bits(base + 0x08, 1, 0); - printk_debug("No codec!\n"); + printk(BIOS_DEBUG, "No codec!\n"); return 0; } @@ -150,7 +150,7 @@ static void codec_init(u32 base, int addr) dword = read32(base + 0x64); /* 2 */ - printk_debug("%x(th) codec viddid: %08x\n", addr, dword); + printk(BIOS_DEBUG, "%x(th) codec viddid: %08x\n", addr, dword); } static void codecs_init(u32 base, u32 codec_mask) @@ -203,11 +203,11 @@ static void hda_init(struct device *dev) return; base = (u32)res->base; - printk_debug("base = 0x%x\n", base); + printk(BIOS_DEBUG, "base = 0x%x\n", base); codec_mask = codec_detect(base); if (codec_mask) { - printk_debug("codec_mask = %02x\n", codec_mask); + printk(BIOS_DEBUG, "codec_mask = %02x\n", codec_mask); codecs_init(base, codec_mask); } } diff --git a/src/southbridge/amd/sb700/sb700_lpc.c b/src/southbridge/amd/sb700/sb700_lpc.c index b6d7818160..3bc160827d 100644 --- a/src/southbridge/amd/sb700/sb700_lpc.c +++ b/src/southbridge/amd/sb700/sb700_lpc.c @@ -143,8 +143,7 @@ static void sb700_lpc_enable_childrens_resources(device_t dev) continue; base = res->base; end = resource_end(res); - printk_debug - ("sb700 lpc decode:%s, base=0x%08x, end=0x%08x\n", + printk(BIOS_DEBUG, "sb700 lpc decode:%s, base=0x%08x, end=0x%08x\n", dev_path(child), base, end); switch (base) { case 0x60: /* KB */ diff --git a/src/southbridge/amd/sb700/sb700_sata.c b/src/southbridge/amd/sb700/sb700_sata.c index cd5084e745..48c192c95d 100644 --- a/src/southbridge/amd/sb700/sb700_sata.c +++ b/src/southbridge/amd/sb700/sb700_sata.c @@ -34,22 +34,22 @@ int sata_drive_detect(int portnum, u16 iobar) while (byte = inb(iobar + 0x6), byte2 = inb(iobar + 0x7), (byte != (0xA0 + 0x10 * (portnum % 2))) || ((byte2 & 0x88) != 0)) { - printk_spew("0x6=%x, 0x7=%x\n", byte, byte2); + printk(BIOS_SPEW, "0x6=%x, 0x7=%x\n", byte, byte2); if (byte != (0xA0 + 0x10 * (portnum % 2))) { /* This will happen at the first iteration of this loop * if the first SATA port is unpopulated and the * second SATA port is poulated. */ - printk_debug("drive no longer selected after %i ms, " + printk(BIOS_DEBUG, "drive no longer selected after %i ms, " "retrying init\n", i * 10); return 1; } else - printk_spew("drive detection not yet completed, " + printk(BIOS_SPEW, "drive detection not yet completed, " "waiting...\n"); mdelay(10); i++; } - printk_spew("drive detection done after %i ms\n", i * 10); + printk(BIOS_SPEW, "drive detection done after %i ms\n", i * 10); return 0; } @@ -96,12 +96,12 @@ static void sata_init(struct device *dev) sata_bar3 = pci_read_config16(dev, 0x1C) & ~0x3; sata_bar4 = pci_read_config16(dev, 0x20) & ~0xf; - printk_spew("sata_bar0=%x\n", sata_bar0); /* 3030 */ - printk_spew("sata_bar1=%x\n", sata_bar1); /* 3070 */ - printk_spew("sata_bar2=%x\n", sata_bar2); /* 3040 */ - printk_spew("sata_bar3=%x\n", sata_bar3); /* 3080 */ - printk_spew("sata_bar4=%x\n", sata_bar4); /* 3000 */ - printk_spew("sata_bar5=%p\n", sata_bar5); /* e0309000 */ + printk(BIOS_SPEW, "sata_bar0=%x\n", sata_bar0); /* 3030 */ + printk(BIOS_SPEW, "sata_bar1=%x\n", sata_bar1); /* 3070 */ + printk(BIOS_SPEW, "sata_bar2=%x\n", sata_bar2); /* 3040 */ + printk(BIOS_SPEW, "sata_bar3=%x\n", sata_bar3); /* 3080 */ + printk(BIOS_SPEW, "sata_bar4=%x\n", sata_bar4); /* 3000 */ + printk(BIOS_SPEW, "sata_bar5=%p\n", sata_bar5); /* e0309000 */ /* disable combined mode */ byte = pci_read_config8(sm_dev, 0xAD); @@ -199,12 +199,12 @@ static void sata_init(struct device *dev) for (i = 0; i < 4; i++) { byte = read8(sata_bar5 + 0x128 + 0x80 * i); - printk_spew("SATA port %i status = %x\n", i, byte); + printk(BIOS_SPEW, "SATA port %i status = %x\n", i, byte); byte &= 0xF; if( byte == 0x1 ) { /* If the drive status is 0x1 then we see it but we aren't talking to it. */ /* Try to do something about it. */ - printk_spew("SATA device detected but not talking. Trying lower speed.\n"); + printk(BIOS_SPEW, "SATA device detected but not talking. Trying lower speed.\n"); /* Read in Port-N Serial ATA Control Register */ byte = read8(sata_bar5 + 0x12C + 0x80 * i); @@ -225,7 +225,7 @@ static void sata_init(struct device *dev) /* Reread status */ byte = read8(sata_bar5 + 0x128 + 0x80 * i); - printk_spew("SATA port %i status = %x\n", i, byte); + printk(BIOS_SPEW, "SATA port %i status = %x\n", i, byte); byte &= 0xF; } @@ -234,13 +234,13 @@ static void sata_init(struct device *dev) if (!sata_drive_detect(i, ((i / 2) == 0) ? sata_bar0 : sata_bar2)) break; } - printk_debug("%s %s device is %sready after %i tries\n", + printk(BIOS_DEBUG, "%s %s device is %sready after %i tries\n", (i / 2) ? "Secondary" : "Primary", (i % 2 ) ? "Slave" : "Master", (j == 10) ? "not " : "", (j == 10) ? j : j + 1); } else { - printk_debug("No %s %s SATA drive on Slot%i\n", + printk(BIOS_DEBUG, "No %s %s SATA drive on Slot%i\n", (i / 2) ? "Secondary" : "Primary", (i % 2 ) ? "Slave" : "Master", i); } @@ -267,7 +267,7 @@ static void sata_init(struct device *dev) /* word = pm_ioread(0x28); */ /* byte = pm_ioread(0x29); */ /* word |= byte<<8; */ - /* printk_debug("AcpiGpe0Blk addr = %x\n", word); */ + /* printk(BIOS_DEBUG, "AcpiGpe0Blk addr = %x\n", word); */ /* write32(word, 0x80000000); */ } diff --git a/src/southbridge/amd/sb700/sb700_sm.c b/src/southbridge/amd/sb700/sb700_sm.c index dbd7a6ab02..d053aff0fd 100644 --- a/src/southbridge/amd/sb700/sb700_sm.c +++ b/src/southbridge/amd/sb700/sb700_sm.c @@ -54,7 +54,7 @@ static void sm_init(device_t dev) u32 on; u32 nmi_option; - printk_info("sm_init().\n"); + printk(BIOS_INFO, "sm_init().\n"); ioapic_base = pci_read_config32(dev, 0x74) & (0xffffffe0); /* some like mem resource, but does not have enable bit */ /* Don't rename APIC ID */ @@ -118,7 +118,7 @@ static void sm_init(device_t dev) } byte |= 1 << 2; pm_iowrite(0x74, byte); - printk_info("set power %s after power fail\n", on ? "on" : "off"); + printk(BIOS_INFO, "set power %s after power fail\n", on ? "on" : "off"); byte = pm_ioread(0x68); byte &= ~(1 << 1); @@ -152,10 +152,10 @@ static void sm_init(device_t dev) get_option(&nmi_option, "nmi"); if (nmi_option) { byte &= ~(1 << 7); /* set NMI */ - printk_info("++++++++++set NMI+++++\n"); + printk(BIOS_INFO, "++++++++++set NMI+++++\n"); } else { byte |= (1 << 7); /* Can not mask NMI from PCI-E and NMI_NOW */ - printk_info("++++++++++no set NMI+++++\n"); + printk(BIOS_INFO, "++++++++++no set NMI+++++\n"); } byte &= ~(1 << 7); if (byte != byte_old) { @@ -217,7 +217,7 @@ static void sm_init(device_t dev) byte &= ~(1 << 1); pm_iowrite(0x59, byte); - printk_info("sm_init() end\n"); + printk(BIOS_INFO, "sm_init() end\n"); /* Enable NbSb virtual channel */ axcfg_reg(0x114, 0x3f << 1, 0 << 1); diff --git a/src/southbridge/amd/sb700/sb700_smbus.c b/src/southbridge/amd/sb700/sb700_smbus.c index 91bbea852d..7ba2a7d264 100644 --- a/src/southbridge/amd/sb700/sb700_smbus.c +++ b/src/southbridge/amd/sb700/sb700_smbus.c @@ -196,7 +196,7 @@ static void alink_ab_indx(u32 reg_space, u32 reg_addr, tmp &= ~mask; tmp |= val; - /* printk_debug("about write %x, index=%x", tmp, (reg_space&0x3)<<30 | reg_addr); */ + /* printk(BIOS_DEBUG, "about write %x, index=%x", tmp, (reg_space&0x3)<<30 | reg_addr); */ outl((reg_space & 0x3) << 30 | reg_addr, AB_INDX); /* probably we dont have to do it again. */ outl(tmp, AB_DATA); reg_addr & 0x10000 ? outl(0, AB_INDX) : NULL; diff --git a/src/southbridge/amd/sb700/sb700_usb.c b/src/southbridge/amd/sb700/sb700_usb.c index 63679b8847..d2dcf852f2 100644 --- a/src/southbridge/amd/sb700/sb700_usb.c +++ b/src/southbridge/amd/sb700/sb700_usb.c @@ -82,7 +82,7 @@ static void usb_init2(struct device *dev) /* pci_write_config32(dev, 0xf8, dword); */ usb2_bar0 = pci_read_config32(dev, 0x10) & ~0xFF; - printk_info("usb2_bar0=0x%x\n", usb2_bar0); + printk(BIOS_INFO, "usb2_bar0=0x%x\n", usb2_bar0); /* RPR6.4 Enables the USB PHY auto calibration resister to match 45ohm resistence */ dword = 0x00020F00; @@ -163,7 +163,7 @@ static void usb_init2(struct device *dev) dword |= 1 << 8; dword &= ~(1 << 27); /* 6.23 */ } - printk_debug("rpr 6.23, final dword=%x\n", dword); + printk(BIOS_DEBUG, "rpr 6.23, final dword=%x\n", dword); #endif } diff --git a/src/southbridge/broadcom/bcm21000/bcm21000_pcie.c b/src/southbridge/broadcom/bcm21000/bcm21000_pcie.c index ef3f4509ee..4027f48e7c 100644 --- a/src/southbridge/broadcom/bcm21000/bcm21000_pcie.c +++ b/src/southbridge/broadcom/bcm21000/bcm21000_pcie.c @@ -33,7 +33,7 @@ static void pcie_init(struct device *dev) uint32_t dword; uint32_t msicap; - printk_debug("PCIE enable.... dev= %s\n",dev_path(dev)); + printk(BIOS_DEBUG, "PCIE enable.... dev= %s\n",dev_path(dev)); /* System error enable */ dword = pci_read_config32(dev, 0x04); diff --git a/src/southbridge/broadcom/bcm5785/bcm5785_lpc.c b/src/southbridge/broadcom/bcm5785/bcm5785_lpc.c index 85f9eaf6c4..481d68c74f 100644 --- a/src/southbridge/broadcom/bcm5785/bcm5785_lpc.c +++ b/src/southbridge/broadcom/bcm5785/bcm5785_lpc.c @@ -86,7 +86,7 @@ static void bcm5785_lpc_enable_childrens_resources(device_t dev) if(!(res->flags & IORESOURCE_IO)) continue; base = res->base; end = resource_end(res); - printk_debug("bcm5785lpc decode:%s, base=0x%08x, end=0x%08x\r\n",dev_path(child),base, end); + printk(BIOS_DEBUG, "bcm5785lpc decode:%s, base=0x%08x, end=0x%08x\r\n",dev_path(child),base, end); switch(base) { case 0x60: //KBC case 0x64: diff --git a/src/southbridge/broadcom/bcm5785/bcm5785_sata.c b/src/southbridge/broadcom/bcm5785/bcm5785_sata.c index 6818e6a2b0..7cd9c27f35 100644 --- a/src/southbridge/broadcom/bcm5785/bcm5785_sata.c +++ b/src/southbridge/broadcom/bcm5785/bcm5785_sata.c @@ -49,17 +49,17 @@ static void sata_init(struct device *dev) //init PHY - printk_debug("init PHY...\n"); + printk(BIOS_DEBUG, "init PHY...\n"); for(i=0; i<4; i++) { mmio = base + 0x100 * i; byte = read8(mmio + 0x40); - printk_debug("port %d PHY status = %02x\r\n", i, byte); + printk(BIOS_DEBUG, "port %d PHY status = %02x\r\n", i, byte); if(byte & 0x4) {// bit 2 is set byte = read8(mmio+0x48); write8(mmio + 0x48, byte | 1); write8(mmio + 0x48, byte & (~1)); byte = read8(mmio + 0x40); - printk_debug("after reset port %d PHY status = %02x\r\n", i, byte); + printk(BIOS_DEBUG, "after reset port %d PHY status = %02x\r\n", i, byte); } } diff --git a/src/southbridge/intel/esb6300/esb6300_ehci.c b/src/southbridge/intel/esb6300/esb6300_ehci.c index 313504866e..8c20c0325f 100644 --- a/src/southbridge/intel/esb6300/esb6300_ehci.c +++ b/src/southbridge/intel/esb6300/esb6300_ehci.c @@ -9,12 +9,12 @@ static void ehci_init(struct device *dev) { uint32_t cmd; - printk_debug("EHCI: Setting up controller.. "); + printk(BIOS_DEBUG, "EHCI: Setting up controller.. "); cmd = pci_read_config32(dev, PCI_COMMAND); pci_write_config32(dev, PCI_COMMAND, cmd | PCI_COMMAND_MASTER); - printk_debug("done.\n"); + printk(BIOS_DEBUG, "done.\n"); } static void ehci_set_subsystem(device_t dev, unsigned vendor, unsigned device) diff --git a/src/southbridge/intel/esb6300/esb6300_ide.c b/src/southbridge/intel/esb6300/esb6300_ide.c index eca8a3fefa..e56393722a 100644 --- a/src/southbridge/intel/esb6300/esb6300_ide.c +++ b/src/southbridge/intel/esb6300/esb6300_ide.c @@ -26,7 +26,7 @@ static void ide_init(struct device *dev) word |= (1 << 15); pci_write_config16(dev, 0x42, word); #endif - printk_debug("IDE Enabled\n"); + printk(BIOS_DEBUG, "IDE Enabled\n"); } static void esb6300_ide_set_subsystem(device_t dev, unsigned vendor, unsigned device) diff --git a/src/southbridge/intel/esb6300/esb6300_lpc.c b/src/southbridge/intel/esb6300/esb6300_lpc.c index 09caeb729f..c25771aa0a 100644 --- a/src/southbridge/intel/esb6300/esb6300_lpc.c +++ b/src/southbridge/intel/esb6300/esb6300_lpc.c @@ -288,7 +288,7 @@ static void lpc_init(struct device *dev) byte |= 1; } pci_write_config8(dev, 0xa4, byte); - printk_info("set power %s after power fail\n", pwr_on?"on":"off"); + printk(BIOS_INFO, "set power %s after power fail\n", pwr_on?"on":"off"); /* Set up the PIRQ */ esb6300_pirq_init(dev); diff --git a/src/southbridge/intel/esb6300/esb6300_sata.c b/src/southbridge/intel/esb6300/esb6300_sata.c index 0bedd93a9a..c26b7c4d12 100644 --- a/src/southbridge/intel/esb6300/esb6300_sata.c +++ b/src/southbridge/intel/esb6300/esb6300_sata.c @@ -13,7 +13,7 @@ static void sata_init(struct device *dev) /* Enable SATA devices */ - printk_debug("SATA init\n"); + printk(BIOS_DEBUG, "SATA init\n"); /* SATA configuration */ pci_write_config8(dev, 0x04, 0x07); pci_write_config8(dev, 0x09, 0x8f); @@ -41,7 +41,7 @@ static void sata_init(struct device *dev) pci_write_config16(dev, 0xa0, 0x0040); pci_write_config32(dev, 0xa4, 0x00220043); - printk_debug("SATA Enabled\n"); + printk(BIOS_DEBUG, "SATA Enabled\n"); } static void esb6300_sata_set_subsystem(device_t dev, unsigned vendor, unsigned device) diff --git a/src/southbridge/intel/esb6300/esb6300_uhci.c b/src/southbridge/intel/esb6300/esb6300_uhci.c index 9184ed24e4..10b1dfa1cc 100644 --- a/src/southbridge/intel/esb6300/esb6300_uhci.c +++ b/src/southbridge/intel/esb6300/esb6300_uhci.c @@ -10,13 +10,13 @@ static void uhci_init(struct device *dev) uint32_t cmd; #if 1 - printk_debug("UHCI: Setting up controller.. "); + printk(BIOS_DEBUG, "UHCI: Setting up controller.. "); cmd = pci_read_config32(dev, PCI_COMMAND); pci_write_config32(dev, PCI_COMMAND, cmd | PCI_COMMAND_MASTER); - printk_debug("done.\n"); + printk(BIOS_DEBUG, "done.\n"); #endif } diff --git a/src/southbridge/intel/i3100/i3100_lpc.c b/src/southbridge/intel/i3100/i3100_lpc.c index 2d3b1fbf6f..4612c916d2 100644 --- a/src/southbridge/intel/i3100/i3100_lpc.c +++ b/src/southbridge/intel/i3100/i3100_lpc.c @@ -232,7 +232,7 @@ static void i3100_power_options(device_t dev) { /* minimum asssertion is 1 to 2 RTCCLK */ reg8 &= ~(1 << 3); pci_write_config8(dev, GEN_PMCON_3, reg8); - printk_info("set power %s after power fail\n", pwr_on ? "on" : "off"); + printk(BIOS_INFO, "set power %s after power fail\n", pwr_on ? "on" : "off"); /* Set up NMI on errors. */ reg8 = inb(0x61); @@ -251,11 +251,11 @@ static void i3100_power_options(device_t dev) { get_option(&nmi_option, "nmi"); if (nmi_option) { /* Set NMI. */ - printk_info ("NMI sources enabled.\n"); + printk(BIOS_INFO, "NMI sources enabled.\n"); reg8 &= ~(1 << 7); } else { /* Can't mask NMI from PCI-E and NMI_NOW */ - printk_info ("NMI sources disabled.\n"); + printk(BIOS_INFO, "NMI sources disabled.\n"); reg8 |= ( 1 << 7); } outb(reg8, 0x70); diff --git a/src/southbridge/intel/i3100/i3100_pciexp_portb.c b/src/southbridge/intel/i3100/i3100_pciexp_portb.c index a987da02f5..31502a46de 100644 --- a/src/southbridge/intel/i3100/i3100_pciexp_portb.c +++ b/src/southbridge/intel/i3100/i3100_pciexp_portb.c @@ -46,12 +46,12 @@ static unsigned int pcie_scan_bridge(struct device *dev, unsigned int max) int flag = 0; do { val = pci_read_config16(dev, PCIE_LSTS); - printk_debug("pcie portb link status: %02x\n", val); + printk(BIOS_DEBUG, "pcie portb link status: %02x\n", val); if ((val & (1<<10)) && (!flag)) { /* training error */ ctl = pci_read_config16(dev, PCIE_LCTL); pci_write_config16(dev, PCIE_LCTL, (ctl | (1<<5))); val = pci_read_config16(dev, PCIE_LSTS); - printk_debug("pcie portb reset link status: %02x\n", val); + printk(BIOS_DEBUG, "pcie portb reset link status: %02x\n", val); flag=1; hard_reset(); } diff --git a/src/southbridge/intel/i3100/i3100_sata.c b/src/southbridge/intel/i3100/i3100_sata.c index a124d10d11..cafb68fe0d 100644 --- a/src/southbridge/intel/i3100/i3100_sata.c +++ b/src/southbridge/intel/i3100/i3100_sata.c @@ -53,7 +53,7 @@ static void sata_init(struct device *dev) ahci = (pci_read_config8(dev, SATA_MAP) >> 6) & 0x03; /* Enable SATA devices */ - printk_info("SATA init (%s mode)\n", ahci ? "AHCI" : "Legacy"); + printk(BIOS_INFO, "SATA init (%s mode)\n", ahci ? "AHCI" : "Legacy"); if(ahci) { /* AHCI mode */ @@ -97,7 +97,7 @@ static void sata_init(struct device *dev) pci_write_config8(dev, SATA_PCS + 1, 0x0f); } - printk_debug("SATA Enabled\n"); + printk(BIOS_DEBUG, "SATA Enabled\n"); } static void sata_set_subsystem(device_t dev, unsigned vendor, unsigned device) diff --git a/src/southbridge/intel/i82371eb/i82371eb_ide.c b/src/southbridge/intel/i82371eb/i82371eb_ide.c index 0e91839fb2..f1b618fa71 100644 --- a/src/southbridge/intel/i82371eb/i82371eb_ide.c +++ b/src/southbridge/intel/i82371eb/i82371eb_ide.c @@ -48,14 +48,14 @@ static void ide_init_enable(struct device *dev) reg16 = pci_read_config16(dev, IDETIM_PRI); reg16 = ONOFF(conf->ide0_enable, reg16, IDE_DECODE_ENABLE); pci_write_config16(dev, IDETIM_PRI, reg16); - printk_debug("IDE: %s: %s\n", "Primary IDE interface", + printk(BIOS_DEBUG, "IDE: %s: %s\n", "Primary IDE interface", conf->ide0_enable ? "on" : "off"); /* Enable/disable the secondary IDE interface. */ reg16 = pci_read_config16(dev, IDETIM_SEC); reg16 = ONOFF(conf->ide1_enable, reg16, IDE_DECODE_ENABLE); pci_write_config16(dev, IDETIM_SEC, reg16); - printk_debug("IDE: %s: %s\n", "Secondary IDE interface", + printk(BIOS_DEBUG, "IDE: %s: %s\n", "Secondary IDE interface", conf->ide1_enable ? "on" : "off"); /* Enable access to the legacy IDE ports (both primary and secondary), @@ -67,7 +67,7 @@ static void ide_init_enable(struct device *dev) reg16 = ONOFF(conf->ide_legacy_enable, reg16, (PCI_COMMAND_IO | PCI_COMMAND_MASTER)); pci_write_config16(dev, PCI_COMMAND, reg16); - printk_debug("IDE: Access to legacy IDE ports: %s\n", + printk(BIOS_DEBUG, "IDE: Access to legacy IDE ports: %s\n", conf->ide_legacy_enable ? "on" : "off"); } } @@ -96,10 +96,10 @@ static void ide_init_udma33(struct device *dev) reg8 = ONOFF(conf->ide0_drive1_udma33_enable, reg8, PSDE1); pci_write_config8(dev, UDMACTL, reg8); - printk_debug("IDE: %s, drive %d: UDMA/33: %s\n", + printk(BIOS_DEBUG, "IDE: %s, drive %d: UDMA/33: %s\n", "Primary IDE interface", 0, conf->ide0_drive0_udma33_enable ? "on" : "off"); - printk_debug("IDE: %s, drive %d: UDMA/33: %s\n", + printk(BIOS_DEBUG, "IDE: %s, drive %d: UDMA/33: %s\n", "Primary IDE interface", 1, conf->ide0_drive1_udma33_enable ? "on" : "off"); } @@ -111,10 +111,10 @@ static void ide_init_udma33(struct device *dev) reg8 = ONOFF(conf->ide1_drive1_udma33_enable, reg8, SSDE1); pci_write_config8(dev, UDMACTL, reg8); - printk_debug("IDE: %s, drive %d: UDMA/33: %s\n", + printk(BIOS_DEBUG, "IDE: %s, drive %d: UDMA/33: %s\n", "Secondary IDE interface", 0, conf->ide1_drive0_udma33_enable ? "on" : "off"); - printk_debug("IDE: %s, drive %d: UDMA/33: %s\n", + printk(BIOS_DEBUG, "IDE: %s, drive %d: UDMA/33: %s\n", "Secondary IDE interface", 1, conf->ide1_drive1_udma33_enable ? "on" : "off"); } diff --git a/src/southbridge/intel/i82801ax/i82801ax_ide.c b/src/southbridge/intel/i82801ax/i82801ax_ide.c index c13fb4d34a..2daa986bd4 100644 --- a/src/southbridge/intel/i82801ax/i82801ax_ide.c +++ b/src/southbridge/intel/i82801ax/i82801ax_ide.c @@ -43,9 +43,9 @@ static void ide_init(struct device *dev) if (!config || config->ide0_enable) { /* Enable primary IDE interface. */ ideTimingConfig |= IDE_DECODE_ENABLE; - printk_debug("IDE0: Primary IDE interface is enabled\n"); + printk(BIOS_DEBUG, "IDE0: Primary IDE interface is enabled\n"); } else { - printk_info("IDE0: Primary IDE interface is disabled\n"); + printk(BIOS_INFO, "IDE0: Primary IDE interface is disabled\n"); } pci_write_config16(dev, IDE_TIM_PRI, ideTimingConfig); @@ -54,9 +54,9 @@ static void ide_init(struct device *dev) if (!config || config->ide1_enable) { /* Enable secondary IDE interface. */ ideTimingConfig |= IDE_DECODE_ENABLE; - printk_debug("IDE1: Secondary IDE interface is enabled\n"); + printk(BIOS_DEBUG, "IDE1: Secondary IDE interface is enabled\n"); } else { - printk_info("IDE1: Secondary IDE interface is disabled\n"); + printk(BIOS_INFO, "IDE1: Secondary IDE interface is disabled\n"); } pci_write_config16(dev, IDE_TIM_SEC, ideTimingConfig); } diff --git a/src/southbridge/intel/i82801ax/i82801ax_lpc.c b/src/southbridge/intel/i82801ax/i82801ax_lpc.c index e42bac3449..3f0323bd0e 100644 --- a/src/southbridge/intel/i82801ax/i82801ax_lpc.c +++ b/src/southbridge/intel/i82801ax/i82801ax_lpc.c @@ -92,14 +92,14 @@ void i82801ax_enable_apic(struct device *dev) reg32 |= (1 << 1); /* Delayed transaction enable */ reg32 |= (1 << 2); /* DMA collection buffer enable */ pci_write_config32(dev, GEN_CNTL, reg32); - printk_debug("IOAPIC Southbridge enabled %x\n", reg32); + printk(BIOS_DEBUG, "IOAPIC Southbridge enabled %x\n", reg32); *ioapic_index = 0; *ioapic_data = (1 << 25); *ioapic_index = 0; reg32 = *ioapic_data; - printk_debug("Southbridge APIC ID = %x\n", reg32); + printk(BIOS_DEBUG, "Southbridge APIC ID = %x\n", reg32); if (reg32 != (1 << 25)) die("APIC Error\n"); @@ -189,7 +189,7 @@ static void i82801ax_power_options(device_t dev) * 1 == S5 Soft Off */ pci_write_config8(dev, GEN_PMCON_3, pwr_on ? 0 : 1); - printk_info("Set power %s if power fails\n", pwr_on ? "on" : "off"); + printk(BIOS_INFO, "Set power %s if power fails\n", pwr_on ? "on" : "off"); /* Set up NMI on errors. */ byte = inb(0x61); diff --git a/src/southbridge/intel/i82801ax/i82801ax_usb_ehci.c b/src/southbridge/intel/i82801ax/i82801ax_usb_ehci.c index a3f7e7c9fd..32a1085a76 100644 --- a/src/southbridge/intel/i82801ax/i82801ax_usb_ehci.c +++ b/src/southbridge/intel/i82801ax/i82801ax_usb_ehci.c @@ -30,11 +30,11 @@ static void usb_ehci_init(struct device *dev) /* TODO: Is any special init really needed? */ uint32_t cmd; - printk_debug("EHCI: Setting up controller.. "); + printk(BIOS_DEBUG, "EHCI: Setting up controller.. "); cmd = pci_read_config32(dev, PCI_COMMAND); pci_write_config32(dev, PCI_COMMAND, cmd | PCI_COMMAND_MASTER); - printk_debug("done.\n"); + printk(BIOS_DEBUG, "done.\n"); } static void usb_ehci_set_subsystem(device_t dev, unsigned vendor, diff --git a/src/southbridge/intel/i82801ax/i82801ax_watchdog.c b/src/southbridge/intel/i82801ax/i82801ax_watchdog.c index aea10e1c7b..fb45f521c5 100644 --- a/src/southbridge/intel/i82801ax/i82801ax_watchdog.c +++ b/src/southbridge/intel/i82801ax/i82801ax_watchdog.c @@ -50,5 +50,5 @@ void watchdog_off(void) outw(0x0008, base + 0x04); outw(0x0002, base + 0x06); - printk_debug("ICH Watchdog disabled\r\n"); + printk(BIOS_DEBUG, "ICH Watchdog disabled\r\n"); } diff --git a/src/southbridge/intel/i82801bx/i82801bx_ide.c b/src/southbridge/intel/i82801bx/i82801bx_ide.c index 9bfab00399..ffbaf80dbd 100644 --- a/src/southbridge/intel/i82801bx/i82801bx_ide.c +++ b/src/southbridge/intel/i82801bx/i82801bx_ide.c @@ -43,9 +43,9 @@ static void ide_init(struct device *dev) if (!config || config->ide0_enable) { /* Enable primary IDE interface. */ ideTimingConfig |= IDE_DECODE_ENABLE; - printk_debug("IDE0: Primary IDE interface is enabled\n"); + printk(BIOS_DEBUG, "IDE0: Primary IDE interface is enabled\n"); } else { - printk_info("IDE0: Primary IDE interface is disabled\n"); + printk(BIOS_INFO, "IDE0: Primary IDE interface is disabled\n"); } pci_write_config16(dev, IDE_TIM_PRI, ideTimingConfig); @@ -54,9 +54,9 @@ static void ide_init(struct device *dev) if (!config || config->ide1_enable) { /* Enable secondary IDE interface. */ ideTimingConfig |= IDE_DECODE_ENABLE; - printk_debug("IDE1: Secondary IDE interface is enabled\n"); + printk(BIOS_DEBUG, "IDE1: Secondary IDE interface is enabled\n"); } else { - printk_info("IDE1: Secondary IDE interface is disabled\n"); + printk(BIOS_INFO, "IDE1: Secondary IDE interface is disabled\n"); } pci_write_config16(dev, IDE_TIM_SEC, ideTimingConfig); } diff --git a/src/southbridge/intel/i82801bx/i82801bx_lpc.c b/src/southbridge/intel/i82801bx/i82801bx_lpc.c index 0d7e09c931..c63de08c2a 100644 --- a/src/southbridge/intel/i82801bx/i82801bx_lpc.c +++ b/src/southbridge/intel/i82801bx/i82801bx_lpc.c @@ -92,14 +92,14 @@ void i82801bx_enable_apic(struct device *dev) reg32 |= (1 << 1); /* Delayed transaction enable */ reg32 |= (1 << 2); /* DMA collection buffer enable */ pci_write_config32(dev, GEN_CNTL, reg32); - printk_debug("IOAPIC Southbridge enabled %x\n", reg32); + printk(BIOS_DEBUG, "IOAPIC Southbridge enabled %x\n", reg32); *ioapic_index = 0; *ioapic_data = (1 << 25); *ioapic_index = 0; reg32 = *ioapic_data; - printk_debug("Southbridge APIC ID = %x\n", reg32); + printk(BIOS_DEBUG, "Southbridge APIC ID = %x\n", reg32); if (reg32 != (1 << 25)) die("APIC Error\n"); @@ -189,7 +189,7 @@ static void i82801bx_power_options(device_t dev) * 1 == S5 Soft Off */ pci_write_config8(dev, GEN_PMCON_3, pwr_on ? 0 : 1); - printk_info("Set power %s if power fails\n", pwr_on ? "on" : "off"); + printk(BIOS_INFO, "Set power %s if power fails\n", pwr_on ? "on" : "off"); /* Set up NMI on errors. */ byte = inb(0x61); diff --git a/src/southbridge/intel/i82801bx/i82801bx_usb_ehci.c b/src/southbridge/intel/i82801bx/i82801bx_usb_ehci.c index 1e885e920d..29034444b4 100644 --- a/src/southbridge/intel/i82801bx/i82801bx_usb_ehci.c +++ b/src/southbridge/intel/i82801bx/i82801bx_usb_ehci.c @@ -30,11 +30,11 @@ static void usb_ehci_init(struct device *dev) /* TODO: Is any special init really needed? */ uint32_t cmd; - printk_debug("EHCI: Setting up controller.. "); + printk(BIOS_DEBUG, "EHCI: Setting up controller.. "); cmd = pci_read_config32(dev, PCI_COMMAND); pci_write_config32(dev, PCI_COMMAND, cmd | PCI_COMMAND_MASTER); - printk_debug("done.\n"); + printk(BIOS_DEBUG, "done.\n"); } static void usb_ehci_set_subsystem(device_t dev, unsigned vendor, diff --git a/src/southbridge/intel/i82801bx/i82801bx_watchdog.c b/src/southbridge/intel/i82801bx/i82801bx_watchdog.c index aea10e1c7b..fb45f521c5 100644 --- a/src/southbridge/intel/i82801bx/i82801bx_watchdog.c +++ b/src/southbridge/intel/i82801bx/i82801bx_watchdog.c @@ -50,5 +50,5 @@ void watchdog_off(void) outw(0x0008, base + 0x04); outw(0x0002, base + 0x06); - printk_debug("ICH Watchdog disabled\r\n"); + printk(BIOS_DEBUG, "ICH Watchdog disabled\r\n"); } diff --git a/src/southbridge/intel/i82801cx/i82801cx_ide.c b/src/southbridge/intel/i82801cx/i82801cx_ide.c index 2506b2f329..74c442c52c 100644 --- a/src/southbridge/intel/i82801cx/i82801cx_ide.c +++ b/src/southbridge/intel/i82801cx/i82801cx_ide.c @@ -18,7 +18,7 @@ static void ide_init(struct device *dev) if (enable_primary) { /* Enable first ide interface */ ideTimingConfig |= IDE_DECODE_ENABLE; - printk_debug("IDE0 "); + printk(BIOS_DEBUG, "IDE0 "); } pci_write_config16(dev, IDE_TIM_PRI, ideTimingConfig); @@ -27,7 +27,7 @@ static void ide_init(struct device *dev) if (enable_secondary) { /* Enable secondary ide interface */ ideTimingConfig |= IDE_DECODE_ENABLE; - printk_debug("IDE1 "); + printk(BIOS_DEBUG, "IDE1 "); } pci_write_config16(dev, IDE_TIM_SEC, ideTimingConfig); } diff --git a/src/southbridge/intel/i82801cx/i82801cx_lpc.c b/src/southbridge/intel/i82801cx/i82801cx_lpc.c index 4785242a79..9ac3e8326b 100644 --- a/src/southbridge/intel/i82801cx/i82801cx_lpc.c +++ b/src/southbridge/intel/i82801cx/i82801cx_lpc.c @@ -35,7 +35,7 @@ void i82801cx_enable_ioapic( struct device *dev) dword |= (1 << 1); /* delay transaction enable */ dword |= (1 << 2); /* DMA collection buf enable */ pci_write_config32(dev, GEN_CNTL, dword); - printk_debug("ioapic southbridge enabled %x\n",dword); + printk(BIOS_DEBUG, "ioapic southbridge enabled %x\n",dword); // Must program the APIC's ID before using it @@ -45,7 +45,7 @@ void i82801cx_enable_ioapic( struct device *dev) // Hang if the ID didn't take (chip not present?) *ioapic_index = 0; dword = *ioapic_data; - printk_debug("Southbridge apic id = %x\n", (dword>>24) & 0xF); + printk(BIOS_DEBUG, "Southbridge apic id = %x\n", (dword>>24) & 0xF); if(dword != (2<<24)) die(""); @@ -105,7 +105,7 @@ void i82801cx_rtc_init(struct device *dev) pmcon3 |= SLEEP_AFTER_POWER_FAIL; } pci_write_config8(dev, GEN_PMCON_3, pmcon3); - printk_info("set power %s after power fail\n", + printk(BIOS_INFO, "set power %s after power fail\n", pwr_on ? "on" : "off"); // See if the Safe Mode jumper is set @@ -177,7 +177,7 @@ static void lpc_init(struct device *dev) else byte |= 1; // Return to S5 pci_write_config8(dev, GEN_PMCON_3, byte); - printk_info("set power %s after power fail\n", pwr_on?"on":"off"); + printk(BIOS_INFO, "set power %s after power fail\n", pwr_on?"on":"off"); /* Set up NMI on errors */ byte = inb(0x61); diff --git a/src/southbridge/intel/i82801cx/i82801cx_usb.c b/src/southbridge/intel/i82801cx/i82801cx_usb.c index 258581a78b..00b668d023 100644 --- a/src/southbridge/intel/i82801cx/i82801cx_usb.c +++ b/src/southbridge/intel/i82801cx/i82801cx_usb.c @@ -10,14 +10,14 @@ static void usb_init(struct device *dev) #if 0 uint32_t cmd; - printk_debug("USB: Setting up controller.. "); + printk(BIOS_DEBUG, "USB: Setting up controller.. "); cmd = pci_read_config32(dev, PCI_COMMAND); pci_write_config32(dev, PCI_COMMAND, cmd | PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE); - printk_debug("done.\n"); + printk(BIOS_DEBUG, "done.\n"); #endif } diff --git a/src/southbridge/intel/i82801dx/i82801dx_ac97.c b/src/southbridge/intel/i82801dx/i82801dx_ac97.c index 10b100beee..ccfccd3421 100644 --- a/src/southbridge/intel/i82801dx/i82801dx_ac97.c +++ b/src/southbridge/intel/i82801dx/i82801dx_ac97.c @@ -101,7 +101,7 @@ static int ac97_semaphore(void) timeout--; } while ((reg8 & 1) && timeout); if (! timeout) { - printk_debug("Timeout!\n"); + printk(BIOS_DEBUG, "Timeout!\n"); } return (!timeout); @@ -123,7 +123,7 @@ static void ac97_audio_init(struct device *dev) u32 reg32; int i; - printk_debug("Initializing AC'97 Audio.\n"); + printk(BIOS_DEBUG, "Initializing AC'97 Audio.\n"); /* top 16 bits are zero, so don't read them */ nabmbar = pci_read_config16(dev, NABMBAR) & 0xfffe; @@ -142,7 +142,7 @@ static void ac97_audio_init(struct device *dev) reg32 = inl(nabmbar + GLOB_STA); if ((reg32 & ((1 << 28) | (1 << 9) | (1 << 8))) == 0) { /* Primary Codec not found */ - printk_debug("No primary codec. Disabling AC'97 Audio.\n"); + printk(BIOS_DEBUG, "No primary codec. Disabling AC'97 Audio.\n"); return; } @@ -152,7 +152,7 @@ static void ac97_audio_init(struct device *dev) outw(0x8000, nambar + MASTER_VOL); ac97_semaphore(); if (inw(nambar + MASTER_VOL) != 0x8000) { - printk_debug("Codec not programmable. Disabling AC'97 Audio.\n"); + printk(BIOS_DEBUG, "Codec not programmable. Disabling AC'97 Audio.\n"); return; } diff --git a/src/southbridge/intel/i82801dx/i82801dx_ide.c b/src/southbridge/intel/i82801dx/i82801dx_ide.c index bf879a9c3c..75350da058 100644 --- a/src/southbridge/intel/i82801dx/i82801dx_ide.c +++ b/src/southbridge/intel/i82801dx/i82801dx_ide.c @@ -40,9 +40,9 @@ static void ide_init(struct device *dev) if (!config || config->ide0_enable) { /* Enable primary IDE interface. */ ideTimingConfig |= IDE_DECODE_ENABLE; - printk_debug("IDE0: Primary IDE interface is enabled\n"); + printk(BIOS_DEBUG, "IDE0: Primary IDE interface is enabled\n"); } else { - printk_info("IDE0: Primary IDE interface is disabled\n"); + printk(BIOS_INFO, "IDE0: Primary IDE interface is disabled\n"); } pci_write_config16(dev, IDE_TIM_PRI, ideTimingConfig); @@ -51,9 +51,9 @@ static void ide_init(struct device *dev) if (!config || config->ide1_enable) { /* Enable secondary IDE interface. */ ideTimingConfig |= IDE_DECODE_ENABLE; - printk_debug("IDE1: Secondary IDE interface is enabled\n"); + printk(BIOS_DEBUG, "IDE1: Secondary IDE interface is enabled\n"); } else { - printk_info("IDE1: Secondary IDE interface is disabled\n"); + printk(BIOS_INFO, "IDE1: Secondary IDE interface is disabled\n"); } pci_write_config16(dev, IDE_TIM_SEC, ideTimingConfig); } diff --git a/src/southbridge/intel/i82801dx/i82801dx_lpc.c b/src/southbridge/intel/i82801dx/i82801dx_lpc.c index a3130e164e..ae522c310b 100644 --- a/src/southbridge/intel/i82801dx/i82801dx_lpc.c +++ b/src/southbridge/intel/i82801dx/i82801dx_lpc.c @@ -53,14 +53,14 @@ static void i82801dx_enable_ioapic(struct device *dev) reg32 |= (1 << 1); /* Delayed transaction enable */ reg32 |= (1 << 2); /* DMA collection buffer enable */ pci_write_config32(dev, GEN_CNTL, reg32); - printk_debug("IOAPIC Southbridge enabled %x\n", reg32); + printk(BIOS_DEBUG, "IOAPIC Southbridge enabled %x\n", reg32); *ioapic_index = 0; *ioapic_data = (1 << 25); *ioapic_index = 0; reg32 = *ioapic_data; - printk_debug("Southbridge APIC ID = %x\n", reg32); + printk(BIOS_DEBUG, "Southbridge APIC ID = %x\n", reg32); if (reg32 != (1 << 25)) die("APIC Error\n"); @@ -107,7 +107,7 @@ static void i82801dx_power_options(device_t dev) * 1 == S5 Soft Off */ pci_write_config8(dev, GEN_PMCON_3, pwr_on ? 0 : 1); - printk_info("Set power %s if power fails\n", pwr_on ? "on" : "off"); + printk(BIOS_INFO, "Set power %s if power fails\n", pwr_on ? "on" : "off"); /* Set up NMI on errors. */ byte = inb(0x61); @@ -198,7 +198,7 @@ static void enable_hpet(struct device *dev) reg32 |= (code << 15); pci_write_config32(dev, GEN_CNTL, reg32); - printk_debug("Enabling HPET @0x%x\n", HPET_ADDR | (code << 12)); + printk(BIOS_DEBUG, "Enabling HPET @0x%x\n", HPET_ADDR | (code << 12)); } static void lpc_init(struct device *dev) diff --git a/src/southbridge/intel/i82801dx/i82801dx_smi.c b/src/southbridge/intel/i82801dx/i82801dx_smi.c index a536d8ba76..a1277b03a4 100644 --- a/src/southbridge/intel/i82801dx/i82801dx_smi.c +++ b/src/southbridge/intel/i82801dx/i82801dx_smi.c @@ -63,16 +63,16 @@ static u16 reset_pm1_status(void) static void dump_pm1_status(u16 pm1_sts) { - printk_debug("PM1_STS: "); - if (pm1_sts & (1 << 15)) printk_debug("WAK "); - if (pm1_sts & (1 << 14)) printk_debug("PCIEXPWAK "); - if (pm1_sts & (1 << 11)) printk_debug("PRBTNOR "); - if (pm1_sts & (1 << 10)) printk_debug("RTC "); - if (pm1_sts & (1 << 8)) printk_debug("PWRBTN "); - if (pm1_sts & (1 << 5)) printk_debug("GBL "); - if (pm1_sts & (1 << 4)) printk_debug("BM "); - if (pm1_sts & (1 << 0)) printk_debug("TMROF "); - printk_debug("\n"); + printk(BIOS_DEBUG, "PM1_STS: "); + if (pm1_sts & (1 << 15)) printk(BIOS_DEBUG, "WAK "); + if (pm1_sts & (1 << 14)) printk(BIOS_DEBUG, "PCIEXPWAK "); + if (pm1_sts & (1 << 11)) printk(BIOS_DEBUG, "PRBTNOR "); + if (pm1_sts & (1 << 10)) printk(BIOS_DEBUG, "RTC "); + if (pm1_sts & (1 << 8)) printk(BIOS_DEBUG, "PWRBTN "); + if (pm1_sts & (1 << 5)) printk(BIOS_DEBUG, "GBL "); + if (pm1_sts & (1 << 4)) printk(BIOS_DEBUG, "BM "); + if (pm1_sts & (1 << 0)) printk(BIOS_DEBUG, "TMROF "); + printk(BIOS_DEBUG, "\n"); } /** @@ -92,28 +92,28 @@ static u32 reset_smi_status(void) static void dump_smi_status(u32 smi_sts) { - printk_debug("SMI_STS: "); - if (smi_sts & (1 << 26)) printk_debug("SPI "); - if (smi_sts & (1 << 25)) printk_debug("EL_SMI "); - if (smi_sts & (1 << 21)) printk_debug("MONITOR "); - if (smi_sts & (1 << 20)) printk_debug("PCI_EXP_SMI "); - if (smi_sts & (1 << 18)) printk_debug("INTEL_USB2 "); - if (smi_sts & (1 << 17)) printk_debug("LEGACY_USB2 "); - if (smi_sts & (1 << 16)) printk_debug("SMBUS_SMI "); - if (smi_sts & (1 << 15)) printk_debug("SERIRQ_SMI "); - if (smi_sts & (1 << 14)) printk_debug("PERIODIC "); - if (smi_sts & (1 << 13)) printk_debug("TCO "); - if (smi_sts & (1 << 12)) printk_debug("DEVMON "); - if (smi_sts & (1 << 11)) printk_debug("MCSMI "); - if (smi_sts & (1 << 10)) printk_debug("GPI "); - if (smi_sts & (1 << 9)) printk_debug("GPE0 "); - if (smi_sts & (1 << 8)) printk_debug("PM1 "); - if (smi_sts & (1 << 6)) printk_debug("SWSMI_TMR "); - if (smi_sts & (1 << 5)) printk_debug("APM "); - if (smi_sts & (1 << 4)) printk_debug("SLP_SMI "); - if (smi_sts & (1 << 3)) printk_debug("LEGACY_USB "); - if (smi_sts & (1 << 2)) printk_debug("BIOS "); - printk_debug("\n"); + printk(BIOS_DEBUG, "SMI_STS: "); + if (smi_sts & (1 << 26)) printk(BIOS_DEBUG, "SPI "); + if (smi_sts & (1 << 25)) printk(BIOS_DEBUG, "EL_SMI "); + if (smi_sts & (1 << 21)) printk(BIOS_DEBUG, "MONITOR "); + if (smi_sts & (1 << 20)) printk(BIOS_DEBUG, "PCI_EXP_SMI "); + if (smi_sts & (1 << 18)) printk(BIOS_DEBUG, "INTEL_USB2 "); + if (smi_sts & (1 << 17)) printk(BIOS_DEBUG, "LEGACY_USB2 "); + if (smi_sts & (1 << 16)) printk(BIOS_DEBUG, "SMBUS_SMI "); + if (smi_sts & (1 << 15)) printk(BIOS_DEBUG, "SERIRQ_SMI "); + if (smi_sts & (1 << 14)) printk(BIOS_DEBUG, "PERIODIC "); + if (smi_sts & (1 << 13)) printk(BIOS_DEBUG, "TCO "); + if (smi_sts & (1 << 12)) printk(BIOS_DEBUG, "DEVMON "); + if (smi_sts & (1 << 11)) printk(BIOS_DEBUG, "MCSMI "); + if (smi_sts & (1 << 10)) printk(BIOS_DEBUG, "GPI "); + if (smi_sts & (1 << 9)) printk(BIOS_DEBUG, "GPE0 "); + if (smi_sts & (1 << 8)) printk(BIOS_DEBUG, "PM1 "); + if (smi_sts & (1 << 6)) printk(BIOS_DEBUG, "SWSMI_TMR "); + if (smi_sts & (1 << 5)) printk(BIOS_DEBUG, "APM "); + if (smi_sts & (1 << 4)) printk(BIOS_DEBUG, "SLP_SMI "); + if (smi_sts & (1 << 3)) printk(BIOS_DEBUG, "LEGACY_USB "); + if (smi_sts & (1 << 2)) printk(BIOS_DEBUG, "BIOS "); + printk(BIOS_DEBUG, "\n"); } @@ -135,25 +135,25 @@ static u32 reset_gpe0_status(void) static void dump_gpe0_status(u32 gpe0_sts) { int i; - printk_debug("GPE0_STS: "); + printk(BIOS_DEBUG, "GPE0_STS: "); for (i=31; i<= 16; i--) { - if (gpe0_sts & (1 << i)) printk_debug("GPIO%d ", (i-16)); + if (gpe0_sts & (1 << i)) printk(BIOS_DEBUG, "GPIO%d ", (i-16)); } - if (gpe0_sts & (1 << 14)) printk_debug("USB4 "); - if (gpe0_sts & (1 << 13)) printk_debug("PME_B0 "); - if (gpe0_sts & (1 << 12)) printk_debug("USB3 "); - if (gpe0_sts & (1 << 11)) printk_debug("PME "); - if (gpe0_sts & (1 << 10)) printk_debug("EL_SCI/BATLOW "); - if (gpe0_sts & (1 << 9)) printk_debug("PCI_EXP "); - if (gpe0_sts & (1 << 8)) printk_debug("RI "); - if (gpe0_sts & (1 << 7)) printk_debug("SMB_WAK "); - if (gpe0_sts & (1 << 6)) printk_debug("TCO_SCI "); - if (gpe0_sts & (1 << 5)) printk_debug("AC97 "); - if (gpe0_sts & (1 << 4)) printk_debug("USB2 "); - if (gpe0_sts & (1 << 3)) printk_debug("USB1 "); - if (gpe0_sts & (1 << 2)) printk_debug("HOT_PLUG "); - if (gpe0_sts & (1 << 0)) printk_debug("THRM "); - printk_debug("\n"); + if (gpe0_sts & (1 << 14)) printk(BIOS_DEBUG, "USB4 "); + if (gpe0_sts & (1 << 13)) printk(BIOS_DEBUG, "PME_B0 "); + if (gpe0_sts & (1 << 12)) printk(BIOS_DEBUG, "USB3 "); + if (gpe0_sts & (1 << 11)) printk(BIOS_DEBUG, "PME "); + if (gpe0_sts & (1 << 10)) printk(BIOS_DEBUG, "EL_SCI/BATLOW "); + if (gpe0_sts & (1 << 9)) printk(BIOS_DEBUG, "PCI_EXP "); + if (gpe0_sts & (1 << 8)) printk(BIOS_DEBUG, "RI "); + if (gpe0_sts & (1 << 7)) printk(BIOS_DEBUG, "SMB_WAK "); + if (gpe0_sts & (1 << 6)) printk(BIOS_DEBUG, "TCO_SCI "); + if (gpe0_sts & (1 << 5)) printk(BIOS_DEBUG, "AC97 "); + if (gpe0_sts & (1 << 4)) printk(BIOS_DEBUG, "USB2 "); + if (gpe0_sts & (1 << 3)) printk(BIOS_DEBUG, "USB1 "); + if (gpe0_sts & (1 << 2)) printk(BIOS_DEBUG, "HOT_PLUG "); + if (gpe0_sts & (1 << 0)) printk(BIOS_DEBUG, "THRM "); + printk(BIOS_DEBUG, "\n"); } @@ -175,11 +175,11 @@ static u16 reset_alt_gp_smi_status(void) static void dump_alt_gp_smi_status(u16 alt_gp_smi_sts) { int i; - printk_debug("ALT_GP_SMI_STS: "); + printk(BIOS_DEBUG, "ALT_GP_SMI_STS: "); for (i=15; i<= 0; i--) { - if (alt_gp_smi_sts & (1 << i)) printk_debug("GPI%d ", (i-16)); + if (alt_gp_smi_sts & (1 << i)) printk(BIOS_DEBUG, "GPI%d ", (i-16)); } - printk_debug("\n"); + printk(BIOS_DEBUG, "\n"); } @@ -205,21 +205,21 @@ static u32 reset_tco_status(void) static void dump_tco_status(u32 tco_sts) { - printk_debug("TCO_STS: "); - if (tco_sts & (1 << 20)) printk_debug("SMLINK_SLV "); - if (tco_sts & (1 << 18)) printk_debug("BOOT "); - if (tco_sts & (1 << 17)) printk_debug("SECOND_TO "); - if (tco_sts & (1 << 16)) printk_debug("INTRD_DET "); - if (tco_sts & (1 << 12)) printk_debug("DMISERR "); - if (tco_sts & (1 << 10)) printk_debug("DMISMI "); - if (tco_sts & (1 << 9)) printk_debug("DMISCI "); - if (tco_sts & (1 << 8)) printk_debug("BIOSWR "); - if (tco_sts & (1 << 7)) printk_debug("NEWCENTURY "); - if (tco_sts & (1 << 3)) printk_debug("TIMEOUT "); - if (tco_sts & (1 << 2)) printk_debug("TCO_INT "); - if (tco_sts & (1 << 1)) printk_debug("SW_TCO "); - if (tco_sts & (1 << 0)) printk_debug("NMI2SMI "); - printk_debug("\n"); + printk(BIOS_DEBUG, "TCO_STS: "); + if (tco_sts & (1 << 20)) printk(BIOS_DEBUG, "SMLINK_SLV "); + if (tco_sts & (1 << 18)) printk(BIOS_DEBUG, "BOOT "); + if (tco_sts & (1 << 17)) printk(BIOS_DEBUG, "SECOND_TO "); + if (tco_sts & (1 << 16)) printk(BIOS_DEBUG, "INTRD_DET "); + if (tco_sts & (1 << 12)) printk(BIOS_DEBUG, "DMISERR "); + if (tco_sts & (1 << 10)) printk(BIOS_DEBUG, "DMISMI "); + if (tco_sts & (1 << 9)) printk(BIOS_DEBUG, "DMISCI "); + if (tco_sts & (1 << 8)) printk(BIOS_DEBUG, "BIOSWR "); + if (tco_sts & (1 << 7)) printk(BIOS_DEBUG, "NEWCENTURY "); + if (tco_sts & (1 << 3)) printk(BIOS_DEBUG, "TIMEOUT "); + if (tco_sts & (1 << 2)) printk(BIOS_DEBUG, "TCO_INT "); + if (tco_sts & (1 << 1)) printk(BIOS_DEBUG, "SW_TCO "); + if (tco_sts & (1 << 0)) printk(BIOS_DEBUG, "NMI2SMI "); + printk(BIOS_DEBUG, "\n"); } @@ -243,14 +243,14 @@ static void smm_relocate(void) u32 smi_en; u16 pm1_en; - printk_debug("Initializing SMM handler..."); + printk(BIOS_DEBUG, "Initializing SMM handler..."); pmbase = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f, 0)), 0x40) & 0xfffc; - printk_spew(" ... pmbase = 0x%04x\n", pmbase); + printk(BIOS_SPEW, " ... pmbase = 0x%04x\n", pmbase); smi_en = inl(pmbase + SMI_EN); if (smi_en & APMC_EN) { - printk_info("SMI# handler already enabled?\n"); + printk(BIOS_INFO, "SMI# handler already enabled?\n"); return; } @@ -258,7 +258,7 @@ static void smm_relocate(void) memcpy((void *)0x38000, &smm_relocation_start, &smm_relocation_end - &smm_relocation_start); - printk_debug("\n"); + printk(BIOS_DEBUG, "\n"); dump_smi_status(reset_smi_status()); dump_pm1_status(reset_pm1_status()); dump_gpe0_status(reset_gpe0_status()); @@ -314,7 +314,7 @@ static void smm_relocate(void) */ /* raise an SMI interrupt */ - printk_spew(" ... raise SMI#\n"); + printk(BIOS_SPEW, " ... raise SMI#\n"); outb(0x00, 0xb2); } @@ -349,7 +349,7 @@ void smm_lock(void) * After running this function, only a full reset can * make the SMM registers writable again. */ - printk_debug("Locking SMM.\n"); + printk(BIOS_DEBUG, "Locking SMM.\n"); pci_write_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), SMRAM, D_LCK | G_SMRAME | C_BASE_SEG); } diff --git a/src/southbridge/intel/i82801dx/i82801dx_smihandler.c b/src/southbridge/intel/i82801dx/i82801dx_smihandler.c index eda2691ecf..107cf80aea 100644 --- a/src/southbridge/intel/i82801dx/i82801dx_smihandler.c +++ b/src/southbridge/intel/i82801dx/i82801dx_smihandler.c @@ -83,18 +83,18 @@ static u16 reset_pm1_status(void) static void dump_pm1_status(u16 pm1_sts) { - printk_spew("PM1_STS: "); - if (pm1_sts & (1 << 15)) printk_spew("WAK "); - if (pm1_sts & (1 << 14)) printk_spew("PCIEXPWAK "); - if (pm1_sts & (1 << 11)) printk_spew("PRBTNOR "); - if (pm1_sts & (1 << 10)) printk_spew("RTC "); - if (pm1_sts & (1 << 8)) printk_spew("PWRBTN "); - if (pm1_sts & (1 << 5)) printk_spew("GBL "); - if (pm1_sts & (1 << 4)) printk_spew("BM "); - if (pm1_sts & (1 << 0)) printk_spew("TMROF "); - printk_spew("\n"); + printk(BIOS_SPEW, "PM1_STS: "); + if (pm1_sts & (1 << 15)) printk(BIOS_SPEW, "WAK "); + if (pm1_sts & (1 << 14)) printk(BIOS_SPEW, "PCIEXPWAK "); + if (pm1_sts & (1 << 11)) printk(BIOS_SPEW, "PRBTNOR "); + if (pm1_sts & (1 << 10)) printk(BIOS_SPEW, "RTC "); + if (pm1_sts & (1 << 8)) printk(BIOS_SPEW, "PWRBTN "); + if (pm1_sts & (1 << 5)) printk(BIOS_SPEW, "GBL "); + if (pm1_sts & (1 << 4)) printk(BIOS_SPEW, "BM "); + if (pm1_sts & (1 << 0)) printk(BIOS_SPEW, "TMROF "); + printk(BIOS_SPEW, "\n"); int reg16 = inw(pmbase + PM1_EN); - printk_spew("PM1_EN: %x\n", reg16); + printk(BIOS_SPEW, "PM1_EN: %x\n", reg16); } /** @@ -114,28 +114,28 @@ static u32 reset_smi_status(void) static void dump_smi_status(u32 smi_sts) { - printk_debug("SMI_STS: "); - if (smi_sts & (1 << 26)) printk_debug("SPI "); - if (smi_sts & (1 << 25)) printk_debug("EL_SMI "); - if (smi_sts & (1 << 21)) printk_debug("MONITOR "); - if (smi_sts & (1 << 20)) printk_debug("PCI_EXP_SMI "); - if (smi_sts & (1 << 18)) printk_debug("INTEL_USB2 "); - if (smi_sts & (1 << 17)) printk_debug("LEGACY_USB2 "); - if (smi_sts & (1 << 16)) printk_debug("SMBUS_SMI "); - if (smi_sts & (1 << 15)) printk_debug("SERIRQ_SMI "); - if (smi_sts & (1 << 14)) printk_debug("PERIODIC "); - if (smi_sts & (1 << 13)) printk_debug("TCO "); - if (smi_sts & (1 << 12)) printk_debug("DEVMON "); - if (smi_sts & (1 << 11)) printk_debug("MCSMI "); - if (smi_sts & (1 << 10)) printk_debug("GPI "); - if (smi_sts & (1 << 9)) printk_debug("GPE0 "); - if (smi_sts & (1 << 8)) printk_debug("PM1 "); - if (smi_sts & (1 << 6)) printk_debug("SWSMI_TMR "); - if (smi_sts & (1 << 5)) printk_debug("APM "); - if (smi_sts & (1 << 4)) printk_debug("SLP_SMI "); - if (smi_sts & (1 << 3)) printk_debug("LEGACY_USB "); - if (smi_sts & (1 << 2)) printk_debug("BIOS "); - printk_debug("\n"); + printk(BIOS_DEBUG, "SMI_STS: "); + if (smi_sts & (1 << 26)) printk(BIOS_DEBUG, "SPI "); + if (smi_sts & (1 << 25)) printk(BIOS_DEBUG, "EL_SMI "); + if (smi_sts & (1 << 21)) printk(BIOS_DEBUG, "MONITOR "); + if (smi_sts & (1 << 20)) printk(BIOS_DEBUG, "PCI_EXP_SMI "); + if (smi_sts & (1 << 18)) printk(BIOS_DEBUG, "INTEL_USB2 "); + if (smi_sts & (1 << 17)) printk(BIOS_DEBUG, "LEGACY_USB2 "); + if (smi_sts & (1 << 16)) printk(BIOS_DEBUG, "SMBUS_SMI "); + if (smi_sts & (1 << 15)) printk(BIOS_DEBUG, "SERIRQ_SMI "); + if (smi_sts & (1 << 14)) printk(BIOS_DEBUG, "PERIODIC "); + if (smi_sts & (1 << 13)) printk(BIOS_DEBUG, "TCO "); + if (smi_sts & (1 << 12)) printk(BIOS_DEBUG, "DEVMON "); + if (smi_sts & (1 << 11)) printk(BIOS_DEBUG, "MCSMI "); + if (smi_sts & (1 << 10)) printk(BIOS_DEBUG, "GPI "); + if (smi_sts & (1 << 9)) printk(BIOS_DEBUG, "GPE0 "); + if (smi_sts & (1 << 8)) printk(BIOS_DEBUG, "PM1 "); + if (smi_sts & (1 << 6)) printk(BIOS_DEBUG, "SWSMI_TMR "); + if (smi_sts & (1 << 5)) printk(BIOS_DEBUG, "APM "); + if (smi_sts & (1 << 4)) printk(BIOS_DEBUG, "SLP_SMI "); + if (smi_sts & (1 << 3)) printk(BIOS_DEBUG, "LEGACY_USB "); + if (smi_sts & (1 << 2)) printk(BIOS_DEBUG, "BIOS "); + printk(BIOS_DEBUG, "\n"); } @@ -157,25 +157,25 @@ static u32 reset_gpe0_status(void) static void dump_gpe0_status(u32 gpe0_sts) { int i; - printk_debug("GPE0_STS: "); + printk(BIOS_DEBUG, "GPE0_STS: "); for (i=31; i<= 16; i--) { - if (gpe0_sts & (1 << i)) printk_debug("GPIO%d ", (i-16)); + if (gpe0_sts & (1 << i)) printk(BIOS_DEBUG, "GPIO%d ", (i-16)); } - if (gpe0_sts & (1 << 14)) printk_debug("USB4 "); - if (gpe0_sts & (1 << 13)) printk_debug("PME_B0 "); - if (gpe0_sts & (1 << 12)) printk_debug("USB3 "); - if (gpe0_sts & (1 << 11)) printk_debug("PME "); - if (gpe0_sts & (1 << 10)) printk_debug("EL_SCI/BATLOW "); - if (gpe0_sts & (1 << 9)) printk_debug("PCI_EXP "); - if (gpe0_sts & (1 << 8)) printk_debug("RI "); - if (gpe0_sts & (1 << 7)) printk_debug("SMB_WAK "); - if (gpe0_sts & (1 << 6)) printk_debug("TCO_SCI "); - if (gpe0_sts & (1 << 5)) printk_debug("AC97 "); - if (gpe0_sts & (1 << 4)) printk_debug("USB2 "); - if (gpe0_sts & (1 << 3)) printk_debug("USB1 "); - if (gpe0_sts & (1 << 2)) printk_debug("HOT_PLUG "); - if (gpe0_sts & (1 << 0)) printk_debug("THRM "); - printk_debug("\n"); + if (gpe0_sts & (1 << 14)) printk(BIOS_DEBUG, "USB4 "); + if (gpe0_sts & (1 << 13)) printk(BIOS_DEBUG, "PME_B0 "); + if (gpe0_sts & (1 << 12)) printk(BIOS_DEBUG, "USB3 "); + if (gpe0_sts & (1 << 11)) printk(BIOS_DEBUG, "PME "); + if (gpe0_sts & (1 << 10)) printk(BIOS_DEBUG, "EL_SCI/BATLOW "); + if (gpe0_sts & (1 << 9)) printk(BIOS_DEBUG, "PCI_EXP "); + if (gpe0_sts & (1 << 8)) printk(BIOS_DEBUG, "RI "); + if (gpe0_sts & (1 << 7)) printk(BIOS_DEBUG, "SMB_WAK "); + if (gpe0_sts & (1 << 6)) printk(BIOS_DEBUG, "TCO_SCI "); + if (gpe0_sts & (1 << 5)) printk(BIOS_DEBUG, "AC97 "); + if (gpe0_sts & (1 << 4)) printk(BIOS_DEBUG, "USB2 "); + if (gpe0_sts & (1 << 3)) printk(BIOS_DEBUG, "USB1 "); + if (gpe0_sts & (1 << 2)) printk(BIOS_DEBUG, "HOT_PLUG "); + if (gpe0_sts & (1 << 0)) printk(BIOS_DEBUG, "THRM "); + printk(BIOS_DEBUG, "\n"); } @@ -200,21 +200,21 @@ static u32 reset_tco_status(void) static void dump_tco_status(u32 tco_sts) { - printk_debug("TCO_STS: "); - if (tco_sts & (1 << 20)) printk_debug("SMLINK_SLV "); - if (tco_sts & (1 << 18)) printk_debug("BOOT "); - if (tco_sts & (1 << 17)) printk_debug("SECOND_TO "); - if (tco_sts & (1 << 16)) printk_debug("INTRD_DET "); - if (tco_sts & (1 << 12)) printk_debug("DMISERR "); - if (tco_sts & (1 << 10)) printk_debug("DMISMI "); - if (tco_sts & (1 << 9)) printk_debug("DMISCI "); - if (tco_sts & (1 << 8)) printk_debug("BIOSWR "); - if (tco_sts & (1 << 7)) printk_debug("NEWCENTURY "); - if (tco_sts & (1 << 3)) printk_debug("TIMEOUT "); - if (tco_sts & (1 << 2)) printk_debug("TCO_INT "); - if (tco_sts & (1 << 1)) printk_debug("SW_TCO "); - if (tco_sts & (1 << 0)) printk_debug("NMI2SMI "); - printk_debug("\n"); + printk(BIOS_DEBUG, "TCO_STS: "); + if (tco_sts & (1 << 20)) printk(BIOS_DEBUG, "SMLINK_SLV "); + if (tco_sts & (1 << 18)) printk(BIOS_DEBUG, "BOOT "); + if (tco_sts & (1 << 17)) printk(BIOS_DEBUG, "SECOND_TO "); + if (tco_sts & (1 << 16)) printk(BIOS_DEBUG, "INTRD_DET "); + if (tco_sts & (1 << 12)) printk(BIOS_DEBUG, "DMISERR "); + if (tco_sts & (1 << 10)) printk(BIOS_DEBUG, "DMISMI "); + if (tco_sts & (1 << 9)) printk(BIOS_DEBUG, "DMISCI "); + if (tco_sts & (1 << 8)) printk(BIOS_DEBUG, "BIOSWR "); + if (tco_sts & (1 << 7)) printk(BIOS_DEBUG, "NEWCENTURY "); + if (tco_sts & (1 << 3)) printk(BIOS_DEBUG, "TIMEOUT "); + if (tco_sts & (1 << 2)) printk(BIOS_DEBUG, "TCO_INT "); + if (tco_sts & (1 << 1)) printk(BIOS_DEBUG, "SW_TCO "); + if (tco_sts & (1 << 0)) printk(BIOS_DEBUG, "NMI2SMI "); + printk(BIOS_DEBUG, "\n"); } /* We are using PCIe accesses for now @@ -227,7 +227,7 @@ int southbridge_io_trap_handler(int smif) { switch (smif) { case 0x32: - printk_debug("OS Init\n"); + printk(BIOS_DEBUG, "OS Init\n"); /* gnvs->smif: * On success, the IO Trap Handler returns 0 * On failure, the IO Trap Handler returns a value != 0 @@ -306,23 +306,23 @@ static void southbridge_smi_sleep(unsigned int node, smm_state_save_area_t *stat /* Figure out SLP_TYP */ reg32 = inl(pmbase + PM1_CNT); - printk_spew("SMI#: SLP = 0x%08x\n", reg32); + printk(BIOS_SPEW, "SMI#: SLP = 0x%08x\n", reg32); slp_typ = (reg32 >> 10) & 7; /* Next, do the deed. */ switch (slp_typ) { - case 0: printk_debug("SMI#: Entering S0 (On)\n"); break; - case 1: printk_debug("SMI#: Entering S1 (Assert STPCLK#)\n"); break; + case 0: printk(BIOS_DEBUG, "SMI#: Entering S0 (On)\n"); break; + case 1: printk(BIOS_DEBUG, "SMI#: Entering S1 (Assert STPCLK#)\n"); break; case 5: - printk_debug("SMI#: Entering S3 (Suspend-To-RAM)\n"); + printk(BIOS_DEBUG, "SMI#: Entering S3 (Suspend-To-RAM)\n"); /* Invalidate the cache before going to S3 */ wbinvd(); break; - case 6: printk_debug("SMI#: Entering S4 (Suspend-To-Disk)\n"); break; + case 6: printk(BIOS_DEBUG, "SMI#: Entering S4 (Suspend-To-Disk)\n"); break; case 7: - printk_debug("SMI#: Entering S5 (Soft Power off)\n"); + printk(BIOS_DEBUG, "SMI#: Entering S5 (Soft Power off)\n"); outl(0, pmbase + GPE0_EN); @@ -340,7 +340,7 @@ static void southbridge_smi_sleep(unsigned int node, smm_state_save_area_t *stat /* also iterates over all bridges on bus 0 */ busmaster_disable_on_bus(0); break; - default: printk_debug("SMI#: ERROR: SLP_TYP reserved\n"); break; + default: printk(BIOS_DEBUG, "SMI#: ERROR: SLP_TYP reserved\n"); break; } /* Write back to the SLP register to cause the originally intended @@ -375,51 +375,51 @@ static void southbridge_smi_apmc(unsigned int node, smm_state_save_area_t *state * some kind of race condition in Linux * and causes a kernel oops */ - printk_debug("C-state control\n"); + printk(BIOS_DEBUG, "C-state control\n"); break; case PST_CONTROL: /* Calling this function seems to cause * some kind of race condition in Linux * and causes a kernel oops */ - printk_debug("P-state control\n"); + printk(BIOS_DEBUG, "P-state control\n"); break; case ACPI_DISABLE: pmctrl = inl(pmbase + PM1_CNT); pmctrl &= ~SCI_EN; outl(pmctrl, pmbase + PM1_CNT); - printk_debug("SMI#: ACPI disabled.\n"); + printk(BIOS_DEBUG, "SMI#: ACPI disabled.\n"); break; case ACPI_ENABLE: pmctrl = inl(pmbase + PM1_CNT); pmctrl |= SCI_EN; outl(pmctrl, pmbase + PM1_CNT); - printk_debug("SMI#: ACPI enabled.\n"); + printk(BIOS_DEBUG, "SMI#: ACPI enabled.\n"); break; case GNVS_UPDATE: if (smm_initialized) { - printk_debug("SMI#: SMM structures already initialized!\n"); + printk(BIOS_DEBUG, "SMI#: SMM structures already initialized!\n"); return; } gnvs = *(global_nvs_t **)0x500; tcg = *(void **)0x504; smi1 = *(void **)0x508; smm_initialized = 1; - printk_debug("SMI#: Setting up structures to %p, %p, %p\n", gnvs, tcg, smi1); + printk(BIOS_DEBUG, "SMI#: Setting up structures to %p, %p, %p\n", gnvs, tcg, smi1); break; case MBI_UPDATE: // FIXME if (mbi_initialized) { - printk_debug("SMI#: mbi already registered!\n"); + printk(BIOS_DEBUG, "SMI#: mbi already registered!\n"); return; } mbi = *(void **)0x500; mbi_len = *(u32 *)0x504; mbi_initialized = 1; - printk_debug("SMI#: Registered MBI at %p (%d bytes)\n", mbi, mbi_len); + printk(BIOS_DEBUG, "SMI#: Registered MBI at %p (%d bytes)\n", mbi, mbi_len); break; default: - printk_debug("SMI#: Unknown function APM_CNT=%02x\n", reg8); + printk(BIOS_DEBUG, "SMI#: Unknown function APM_CNT=%02x\n", reg8); } } @@ -463,7 +463,7 @@ static void southbridge_smi_gpi(unsigned int node, smm_state_save_area_t *state_ mainboard_smi_gpi(reg16); } else { if (reg16) - printk_debug("GPI (mask %04x)\n",reg16); + printk(BIOS_DEBUG, "GPI (mask %04x)\n",reg16); } } @@ -477,7 +477,7 @@ static void southbridge_smi_mc(unsigned int node, smm_state_save_area_t *state_s if ((reg32 & MCSMI_EN) == 0) return; - printk_debug("Microcontroller SMI.\n"); + printk(BIOS_DEBUG, "Microcontroller SMI.\n"); } @@ -508,12 +508,12 @@ static void southbridge_smi_tco(unsigned int node, smm_state_save_area_t *state_ * resolute answer would be to power down the * box. */ - printk_debug("Switching back to RO\n"); + printk(BIOS_DEBUG, "Switching back to RO\n"); pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xdc, (bios_cntl & ~1)); } /* No else for now? */ } else if (tco_sts & (1 << 3)) { /* TIMEOUT */ /* Handle TCO timeout */ - printk_debug("TCO Timeout.\n"); + printk(BIOS_DEBUG, "TCO Timeout.\n"); } else if (!tco_sts) { dump_tco_status(tco_sts); } @@ -529,7 +529,7 @@ static void southbridge_smi_periodic(unsigned int node, smm_state_save_area_t *s if ((reg32 & PERIODIC_EN) == 0) return; - printk_debug("Periodic SMI.\n"); + printk(BIOS_DEBUG, "Periodic SMI.\n"); } static void southbridge_smi_monitor(unsigned int node, smm_state_save_area_t *state_save) @@ -563,7 +563,7 @@ static void southbridge_smi_monitor(unsigned int node, smm_state_save_area_t *st /* IOTRAP(0) SMIC */ if (IOTRAP(0)) { if (!(trap_cycle & (1 << 24))) { // It's a write - printk_debug("SMI1 command\n"); + printk(BIOS_DEBUG, "SMI1 command\n"); data = RCBA32(0x1e18); data &= mask; // if (smi1) @@ -573,16 +573,16 @@ static void southbridge_smi_monitor(unsigned int node, smm_state_save_area_t *st // Fall through to debug } - printk_debug(" trapped io address = 0x%x\n", trap_cycle & 0xfffc); - for (i=0; i < 4; i++) if(IOTRAP(i)) printk_debug(" TRAPÂ = %d\n", i); - printk_debug(" AHBE = %x\n", (trap_cycle >> 16) & 0xf); - printk_debug(" MASK = 0x%08x\n", mask); - printk_debug(" read/write: %s\n", (trap_cycle & (1 << 24)) ? "read" : "write"); + printk(BIOS_DEBUG, " trapped io address = 0x%x\n", trap_cycle & 0xfffc); + for (i=0; i < 4; i++) if(IOTRAP(i)) printk(BIOS_DEBUG, " TRAPÂ = %d\n", i); + printk(BIOS_DEBUG, " AHBE = %x\n", (trap_cycle >> 16) & 0xf); + printk(BIOS_DEBUG, " MASK = 0x%08x\n", mask); + printk(BIOS_DEBUG, " read/write: %s\n", (trap_cycle & (1 << 24)) ? "read" : "write"); if (!(trap_cycle & (1 << 24))) { /* Write Cycle */ data = RCBA32(0x1e18); - printk_debug(" iotrap written data = 0x%08x\n", data); + printk(BIOS_DEBUG, " iotrap written data = 0x%08x\n", data); } #endif #undef IOTRAP @@ -655,7 +655,7 @@ void southbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_sav if (southbridge_smi[i]) southbridge_smi[i](node, state_save); else { - printk_debug("SMI_STS[%d] occured, but no " + printk(BIOS_DEBUG, "SMI_STS[%d] occured, but no " "handler available.\n", i); dump = 1; } diff --git a/src/southbridge/intel/i82801dx/i82801dx_usb.c b/src/southbridge/intel/i82801dx/i82801dx_usb.c index 48b990d1ac..be44a293dc 100644 --- a/src/southbridge/intel/i82801dx/i82801dx_usb.c +++ b/src/southbridge/intel/i82801dx/i82801dx_usb.c @@ -29,12 +29,12 @@ static void usb_init(struct device *dev) { u32 cmd; - printk_debug("USB: Setting up controller.. "); + printk(BIOS_DEBUG, "USB: Setting up controller.. "); cmd = pci_read_config32(dev, PCI_COMMAND); pci_write_config32(dev, PCI_COMMAND, cmd | PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE); - printk_debug("done.\n"); + printk(BIOS_DEBUG, "done.\n"); } static struct device_operations usb_ops = { diff --git a/src/southbridge/intel/i82801dx/i82801dx_usb2.c b/src/southbridge/intel/i82801dx/i82801dx_usb2.c index 96bbd7748d..a0ea5f64e1 100644 --- a/src/southbridge/intel/i82801dx/i82801dx_usb2.c +++ b/src/southbridge/intel/i82801dx/i82801dx_usb2.c @@ -29,12 +29,12 @@ static void usb2_init(struct device *dev) { u32 cmd; - printk_debug("USB: Setting up controller.. "); + printk(BIOS_DEBUG, "USB: Setting up controller.. "); cmd = pci_read_config32(dev, PCI_COMMAND); pci_write_config32(dev, PCI_COMMAND, cmd | PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE); - printk_debug("done.\n"); + printk(BIOS_DEBUG, "done.\n"); } static struct device_operations usb2_ops = { diff --git a/src/southbridge/intel/i82801ex/i82801ex_ehci.c b/src/southbridge/intel/i82801ex/i82801ex_ehci.c index 60b1f304c2..17da5d94c6 100644 --- a/src/southbridge/intel/i82801ex/i82801ex_ehci.c +++ b/src/southbridge/intel/i82801ex/i82801ex_ehci.c @@ -9,12 +9,12 @@ static void ehci_init(struct device *dev) { uint32_t cmd; - printk_debug("EHCI: Setting up controller.. "); + printk(BIOS_DEBUG, "EHCI: Setting up controller.. "); cmd = pci_read_config32(dev, PCI_COMMAND); pci_write_config32(dev, PCI_COMMAND, cmd | PCI_COMMAND_MASTER); - printk_debug("done.\n"); + printk(BIOS_DEBUG, "done.\n"); } static void ehci_set_subsystem(device_t dev, unsigned vendor, unsigned device) diff --git a/src/southbridge/intel/i82801ex/i82801ex_ide.c b/src/southbridge/intel/i82801ex/i82801ex_ide.c index b4d2311e0b..cd622907ab 100644 --- a/src/southbridge/intel/i82801ex/i82801ex_ide.c +++ b/src/southbridge/intel/i82801ex/i82801ex_ide.c @@ -13,7 +13,7 @@ static void ide_init(struct device *dev) pci_write_config8(dev, 0x48, 0x05); pci_write_config16(dev, 0x4a, 0x0101); pci_write_config16(dev, 0x54, 0x5055); - printk_debug("IDE Enabled\n"); + printk(BIOS_DEBUG, "IDE Enabled\n"); } static void i82801ex_ide_set_subsystem(device_t dev, unsigned vendor, unsigned device) diff --git a/src/southbridge/intel/i82801ex/i82801ex_lpc.c b/src/southbridge/intel/i82801ex/i82801ex_lpc.c index b9d19074a4..b97af3860a 100644 --- a/src/southbridge/intel/i82801ex/i82801ex_lpc.c +++ b/src/southbridge/intel/i82801ex/i82801ex_lpc.c @@ -233,7 +233,7 @@ static void enable_hpet(struct device *dev) dword |= (code<<15); pci_write_config32(dev, GEN_CNTL, dword); - printk_debug("enabling HPET @0x%lx\n", hpet_address | (code <<12) ); + printk(BIOS_DEBUG, "enabling HPET @0x%lx\n", hpet_address | (code <<12) ); } static void lpc_init(struct device *dev) @@ -267,7 +267,7 @@ static void lpc_init(struct device *dev) byte |= 1; } pci_write_config8(dev, 0xa4, byte); - printk_info("set power %s after power fail\n", pwr_on?"on":"off"); + printk(BIOS_INFO, "set power %s after power fail\n", pwr_on?"on":"off"); /* Set up the PIRQ */ i82801ex_pirq_init(dev); diff --git a/src/southbridge/intel/i82801ex/i82801ex_sata.c b/src/southbridge/intel/i82801ex/i82801ex_sata.c index 73f5773fd5..a490f2a8c3 100644 --- a/src/southbridge/intel/i82801ex/i82801ex_sata.c +++ b/src/southbridge/intel/i82801ex/i82801ex_sata.c @@ -7,7 +7,7 @@ static void sata_init(struct device *dev) { - printk_debug("SATA init\n"); + printk(BIOS_DEBUG, "SATA init\n"); /* SATA configuration */ pci_write_config8(dev, 0x04, 0x07); pci_write_config8(dev, 0x09, 0x8f); diff --git a/src/southbridge/intel/i82801ex/i82801ex_uhci.c b/src/southbridge/intel/i82801ex/i82801ex_uhci.c index 177b82089c..fe80079d09 100644 --- a/src/southbridge/intel/i82801ex/i82801ex_uhci.c +++ b/src/southbridge/intel/i82801ex/i82801ex_uhci.c @@ -10,13 +10,13 @@ static void uhci_init(struct device *dev) uint32_t cmd; #if 1 - printk_debug("UHCI: Setting up controller.. "); + printk(BIOS_DEBUG, "UHCI: Setting up controller.. "); cmd = pci_read_config32(dev, PCI_COMMAND); pci_write_config32(dev, PCI_COMMAND, cmd | PCI_COMMAND_MASTER); - printk_debug("done.\n"); + printk(BIOS_DEBUG, "done.\n"); #endif } diff --git a/src/southbridge/intel/i82801ex/i82801ex_watchdog.c b/src/southbridge/intel/i82801ex/i82801ex_watchdog.c index 44a701823a..205ea87d94 100644 --- a/src/southbridge/intel/i82801ex/i82801ex_watchdog.c +++ b/src/southbridge/intel/i82801ex/i82801ex_watchdog.c @@ -24,6 +24,6 @@ void watchdog_off(void) /* Clear TCO timeout status */ outw(0x0008, base + 0x04); outw(0x0002, base + 0x06); - printk_debug("Watchdog ICH5 disabled\r\n"); + printk(BIOS_DEBUG, "Watchdog ICH5 disabled\r\n"); } diff --git a/src/southbridge/intel/i82801gx/i82801gx_ac97.c b/src/southbridge/intel/i82801gx/i82801gx_ac97.c index f1e410715b..602014bb2e 100644 --- a/src/southbridge/intel/i82801gx/i82801gx_ac97.c +++ b/src/southbridge/intel/i82801gx/i82801gx_ac97.c @@ -101,7 +101,7 @@ static int ac97_semaphore(void) timeout--; } while ((reg8 & 1) && timeout); if (! timeout) { - printk_debug("Timeout!\n"); + printk(BIOS_DEBUG, "Timeout!\n"); } return (!timeout); @@ -123,7 +123,7 @@ static void ac97_audio_init(struct device *dev) u32 reg32; int i; - printk_debug("Initializing AC'97 Audio.\n"); + printk(BIOS_DEBUG, "Initializing AC'97 Audio.\n"); /* top 16 bits are zero, so don't read them */ nabmbar = pci_read_config16(dev, NABMBAR) & 0xfffe; @@ -142,7 +142,7 @@ static void ac97_audio_init(struct device *dev) reg32 = inl(nabmbar + GLOB_STA); if ((reg32 & ((1 << 28) | (1 << 9) | (1 << 8))) == 0) { /* Primary Codec not found */ - printk_debug("No primary codec. Disabling AC'97 Audio.\n"); + printk(BIOS_DEBUG, "No primary codec. Disabling AC'97 Audio.\n"); return; } @@ -152,7 +152,7 @@ static void ac97_audio_init(struct device *dev) outw(0x8000, nambar + MASTER_VOL); ac97_semaphore(); if (inw(nambar + MASTER_VOL) != 0x8000) { - printk_debug("Codec not programmable. Disabling AC'97 Audio.\n"); + printk(BIOS_DEBUG, "Codec not programmable. Disabling AC'97 Audio.\n"); return; } diff --git a/src/southbridge/intel/i82801gx/i82801gx_azalia.c b/src/southbridge/intel/i82801gx/i82801gx_azalia.c index 60b7334c2c..a4cf14c4f9 100644 --- a/src/southbridge/intel/i82801gx/i82801gx_azalia.c +++ b/src/southbridge/intel/i82801gx/i82801gx_azalia.c @@ -86,7 +86,7 @@ no_codec: /* Codec Not found */ /* Put HDA back in reset (BAR + 0x8) [0] */ set_bits(base + 0x08, 1, 0); - printk_debug("Azalia: No codec!\n"); + printk(BIOS_DEBUG, "Azalia: No codec!\n"); return 0; } @@ -170,7 +170,7 @@ static void codec_init(struct device *dev, u32 base, int addr) u32 verb_size; int i; - printk_debug("Azalia: Initializing codec #%d\n", addr); + printk(BIOS_DEBUG, "Azalia: Initializing codec #%d\n", addr); /* 1 */ if (wait_for_ready(base) == -1) @@ -185,14 +185,14 @@ static void codec_init(struct device *dev, u32 base, int addr) reg32 = read32(base + 0x64); /* 2 */ - printk_debug("Azalia: codec viddid: %08x\n", reg32); + printk(BIOS_DEBUG, "Azalia: codec viddid: %08x\n", reg32); verb_size = find_verb(dev, reg32, &verb); if (!verb_size) { - printk_debug("Azalia: No verb!\n"); + printk(BIOS_DEBUG, "Azalia: No verb!\n"); return; } - printk_debug("Azalia: verb_size: %d\n", verb_size); + printk(BIOS_DEBUG, "Azalia: verb_size: %d\n", verb_size); /* 3 */ for (i = 0; i < verb_size; i++) { @@ -204,7 +204,7 @@ static void codec_init(struct device *dev, u32 base, int addr) if (wait_for_valid(base) == -1) return; } - printk_debug("Azalia: verb loaded.\n"); + printk(BIOS_DEBUG, "Azalia: verb loaded.\n"); } static void codecs_init(struct device *dev, u32 base, u32 codec_mask) @@ -275,7 +275,7 @@ static void azalia_init(struct device *dev) pci_write_config8(dev, 0x40, reg8); mdelay(1); reg8 = pci_read_config8(dev, 0x40); - printk_debug("Azalia: codec type: %s\n", (reg8 & (1 << 1))?"Azalia":"AC97"); + printk(BIOS_DEBUG, "Azalia: codec type: %s\n", (reg8 & (1 << 1))?"Azalia":"AC97"); // reg8 = pci_read_config8(dev, 0x40); // Audio Control @@ -304,11 +304,11 @@ static void azalia_init(struct device *dev) // NOTE this will break as soon as the Azalia get's a bar above // 4G. Is there anything we can do about it? base = (u32)res->base; - printk_debug("Azalia: base = %08x\n", (u32)base); + printk(BIOS_DEBUG, "Azalia: base = %08x\n", (u32)base); codec_mask = codec_detect(base); if (codec_mask) { - printk_debug("Azalia: codec_mask = %02x\n", codec_mask); + printk(BIOS_DEBUG, "Azalia: codec_mask = %02x\n", codec_mask); codecs_init(dev, base, codec_mask); } } diff --git a/src/southbridge/intel/i82801gx/i82801gx_ide.c b/src/southbridge/intel/i82801gx/i82801gx_ide.c index 28a1c055ea..84b50d6535 100644 --- a/src/southbridge/intel/i82801gx/i82801gx_ide.c +++ b/src/southbridge/intel/i82801gx/i82801gx_ide.c @@ -35,9 +35,9 @@ static void ide_init(struct device *dev) /* Get the chip configuration */ config_t *config = dev->chip_info; - printk_debug("i82801gx_ide: initializing... "); + printk(BIOS_DEBUG, "i82801gx_ide: initializing... "); if (config == NULL) { - printk_err("\ni82801gx_ide: Not mentioned in mainboard's Config.lb!\n"); + printk(BIOS_ERR, "\ni82801gx_ide: Not mentioned in mainboard's Config.lb!\n"); // Trying to set somewhat safe defaults instead of bailing out. enable_primary = enable_secondary = 1; } else { @@ -61,7 +61,7 @@ static void ide_init(struct device *dev) ideTimingConfig |= (3 << 8); // RCT = 1 clock ideTimingConfig |= (1 << 1); // IE0 ideTimingConfig |= (1 << 0); // TIME0 - printk_debug("IDE0 "); + printk(BIOS_DEBUG, "IDE0 "); } pci_write_config16(dev, IDE_TIM_PRI, ideTimingConfig); @@ -75,7 +75,7 @@ static void ide_init(struct device *dev) ideTimingConfig |= (3 << 8); // RCT = 1 clock ideTimingConfig |= (1 << 1); // IE0 ideTimingConfig |= (1 << 0); // TIME0 - printk_debug("IDE1 "); + printk(BIOS_DEBUG, "IDE1 "); } pci_write_config16(dev, IDE_TIM_SEC, ideTimingConfig); @@ -92,7 +92,7 @@ static void ide_init(struct device *dev) /* Interrupt Pin is set by D31IP.PIP */ pci_write_config32(dev, INTR_LN, 0xff); /* Int 15 */ - printk_debug("\n"); + printk(BIOS_DEBUG, "\n"); } static void ide_set_subsystem(device_t dev, unsigned vendor, unsigned device) diff --git a/src/southbridge/intel/i82801gx/i82801gx_lpc.c b/src/southbridge/intel/i82801gx/i82801gx_lpc.c index ccab5482c9..f0e48ec29e 100644 --- a/src/southbridge/intel/i82801gx/i82801gx_lpc.c +++ b/src/southbridge/intel/i82801gx/i82801gx_lpc.c @@ -52,16 +52,16 @@ static void i82801gx_enable_apic(struct device *dev) *ioapic_index = 0; reg32 = *ioapic_data; - printk_debug("Southbridge APIC ID = %x\n", (reg32 >> 24) & 0x0f); + printk(BIOS_DEBUG, "Southbridge APIC ID = %x\n", (reg32 >> 24) & 0x0f); if (reg32 != (1 << 25)) die("APIC Error\n"); - printk_spew("Dumping IOAPIC registers\n"); + printk(BIOS_SPEW, "Dumping IOAPIC registers\n"); for (i=0; i<3; i++) { *ioapic_index = i; - printk_spew(" reg 0x%04x:", i); + printk(BIOS_SPEW, " reg 0x%04x:", i); reg32 = *ioapic_data; - printk_spew(" 0x%08x\n", reg32); + printk(BIOS_SPEW, " 0x%08x\n", reg32); } *ioapic_index = 3; /* Select Boot Configuration register. */ @@ -213,7 +213,7 @@ static void i82801gx_power_options(device_t dev) reg8 &= ~(1 << 3); /* minimum asssertion is 1 to 2 RTCCLK */ pci_write_config8(dev, GEN_PMCON_3, reg8); - printk_info("Set power %s after power failure.\n", state); + printk(BIOS_INFO, "Set power %s after power failure.\n", state); /* Set up NMI on errors. */ reg8 = inb(0x61); @@ -227,10 +227,10 @@ static void i82801gx_power_options(device_t dev) nmi_option = NMI_OFF; get_option(&nmi_option, "nmi"); if (nmi_option) { - printk_info ("NMI sources enabled.\n"); + printk(BIOS_INFO, "NMI sources enabled.\n"); reg8 &= ~(1 << 7); /* Set NMI. */ } else { - printk_info ("NMI sources disabled.\n"); + printk(BIOS_INFO, "NMI sources disabled.\n"); reg8 |= ( 1 << 7); /* Can't mask NMI from PCI-E and NMI_NOW */ } outb(reg8, 0x70); @@ -296,7 +296,7 @@ static void i82801gx_rtc_init(struct device *dev) reg8 &= ~RTC_BATTERY_DEAD; pci_write_config8(dev, GEN_PMCON_3, reg8); } - printk_debug("rtc_failed = 0x%x\n", rtc_failed); + printk(BIOS_DEBUG, "rtc_failed = 0x%x\n", rtc_failed); rtc_init(rtc_failed); } @@ -340,13 +340,13 @@ static void i82801gx_lock_smm(struct device *dev) #endif #if ENABLE_ACPI_MODE_IN_COREBOOT - printk_debug("Enabling ACPI via APMC:\n"); + printk(BIOS_DEBUG, "Enabling ACPI via APMC:\n"); outb(0xe1, 0xb2); // Enable ACPI mode - printk_debug("done.\n"); + printk(BIOS_DEBUG, "done.\n"); #else - printk_debug("Disabling ACPI via APMC:\n"); + printk(BIOS_DEBUG, "Disabling ACPI via APMC:\n"); outb(0x1e, 0xb2); // Disable ACPI mode - printk_debug("done.\n"); + printk(BIOS_DEBUG, "done.\n"); #endif /* Don't allow evil boot loaders, kernels, or * userspace applications to deceive us: @@ -355,29 +355,29 @@ static void i82801gx_lock_smm(struct device *dev) #if TEST_SMM_FLASH_LOCKDOWN /* Now try this: */ - printk_debug("Locking BIOS to RO... "); + printk(BIOS_DEBUG, "Locking BIOS to RO... "); reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */ - printk_debug(" BLE: %s; BWE: %s\n", (reg8&2)?"on":"off", + printk(BIOS_DEBUG, " BLE: %s; BWE: %s\n", (reg8&2)?"on":"off", (reg8&1)?"rw":"ro"); reg8 &= ~(1 << 0); /* clear BIOSWE */ pci_write_config8(dev, 0xdc, reg8); reg8 |= (1 << 1); /* set BLE */ pci_write_config8(dev, 0xdc, reg8); - printk_debug("ok.\n"); + printk(BIOS_DEBUG, "ok.\n"); reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */ - printk_debug(" BLE: %s; BWE: %s\n", (reg8&2)?"on":"off", + printk(BIOS_DEBUG, " BLE: %s; BWE: %s\n", (reg8&2)?"on":"off", (reg8&1)?"rw":"ro"); - printk_debug("Writing:\n"); + printk(BIOS_DEBUG, "Writing:\n"); *(volatile u8 *)0xfff00000 = 0x00; - printk_debug("Testing:\n"); + printk(BIOS_DEBUG, "Testing:\n"); reg8 |= (1 << 0); /* set BIOSWE */ pci_write_config8(dev, 0xdc, reg8); reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */ - printk_debug(" BLE: %s; BWE: %s\n", (reg8&2)?"on":"off", + printk(BIOS_DEBUG, " BLE: %s; BWE: %s\n", (reg8&2)?"on":"off", (reg8&1)?"rw":"ro"); - printk_debug("Done.\n"); + printk(BIOS_DEBUG, "Done.\n"); #endif } #endif @@ -406,7 +406,7 @@ static void i82801gx_fixups(struct device *dev) static void lpc_init(struct device *dev) { - printk_debug("i82801gx: lpc_init\n"); + printk(BIOS_DEBUG, "i82801gx: lpc_init\n"); /* Set the value for PCI command register. */ pci_write_config16(dev, PCI_COMMAND, 0x000f); diff --git a/src/southbridge/intel/i82801gx/i82801gx_pci.c b/src/southbridge/intel/i82801gx/i82801gx_pci.c index d9057cb295..c4c22f0ae8 100644 --- a/src/southbridge/intel/i82801gx/i82801gx_pci.c +++ b/src/southbridge/intel/i82801gx/i82801gx_pci.c @@ -71,7 +71,7 @@ static void ich_pci_dev_enable_resources(struct device *dev) /* Set the subsystem vendor and device id for mainboard devices */ ops = ops_pci(dev); if (dev->on_mainboard && ops && ops->set_subsystem) { - printk_debug("%s subsystem <- %02x/%02x\n", + printk(BIOS_DEBUG, "%s subsystem <- %02x/%02x\n", dev_path(dev), CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID, CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID); @@ -87,10 +87,10 @@ static void ich_pci_dev_enable_resources(struct device *dev) * this will cause the ROM and APICs not being visible * anymore. */ - printk_debug("%s cmd <- %02x\n", dev_path(dev), command); + printk(BIOS_DEBUG, "%s cmd <- %02x\n", dev_path(dev), command); pci_write_config16(dev, PCI_COMMAND, command); #else - printk_debug("%s cmd <- %02x (NOT WRITTEN!)\n", dev_path(dev), command); + printk(BIOS_DEBUG, "%s cmd <- %02x (NOT WRITTEN!)\n", dev_path(dev), command); #endif } @@ -105,7 +105,7 @@ static void ich_pci_bus_enable_resources(struct device *dev) ctrl = pci_read_config16(dev, PCI_BRIDGE_CONTROL); ctrl |= dev->link[0].bridge_ctrl; ctrl |= (PCI_BRIDGE_CTL_PARITY + PCI_BRIDGE_CTL_SERR); /* error check */ - printk_debug("%s bridge ctrl <- %04x\n", dev_path(dev), ctrl); + printk(BIOS_DEBUG, "%s bridge ctrl <- %04x\n", dev_path(dev), ctrl); pci_write_config16(dev, PCI_BRIDGE_CONTROL, ctrl); /* This is the reason we need our own pci_bus_enable_resources */ diff --git a/src/southbridge/intel/i82801gx/i82801gx_pcie.c b/src/southbridge/intel/i82801gx/i82801gx_pcie.c index b66a887063..d69bc6d07d 100644 --- a/src/southbridge/intel/i82801gx/i82801gx_pcie.c +++ b/src/southbridge/intel/i82801gx/i82801gx_pcie.c @@ -28,7 +28,7 @@ static void pci_init(struct device *dev) u16 reg16; u32 reg32; - printk_debug("Initializing ICH7 PCIe bridge.\n"); + printk(BIOS_DEBUG, "Initializing ICH7 PCIe bridge.\n"); /* Enable Bus Master */ reg32 = pci_read_config32(dev, PCI_COMMAND); @@ -77,13 +77,13 @@ static void pci_init(struct device *dev) #ifdef EVEN_MORE_DEBUG reg32 = pci_read_config32(dev, 0x20); - printk_spew(" MBL = 0x%08x\n", reg32); + printk(BIOS_SPEW, " MBL = 0x%08x\n", reg32); reg32 = pci_read_config32(dev, 0x24); - printk_spew(" PMBL = 0x%08x\n", reg32); + printk(BIOS_SPEW, " PMBL = 0x%08x\n", reg32); reg32 = pci_read_config32(dev, 0x28); - printk_spew(" PMBU32 = 0x%08x\n", reg32); + printk(BIOS_SPEW, " PMBU32 = 0x%08x\n", reg32); reg32 = pci_read_config32(dev, 0x2c); - printk_spew(" PMLU32 = 0x%08x\n", reg32); + printk(BIOS_SPEW, " PMLU32 = 0x%08x\n", reg32); #endif /* Clear errors in status registers */ diff --git a/src/southbridge/intel/i82801gx/i82801gx_sata.c b/src/southbridge/intel/i82801gx/i82801gx_sata.c index ec477e1696..50cdb48131 100644 --- a/src/southbridge/intel/i82801gx/i82801gx_sata.c +++ b/src/southbridge/intel/i82801gx/i82801gx_sata.c @@ -33,10 +33,10 @@ static void sata_init(struct device *dev) /* Get the chip configuration */ config_t *config = dev->chip_info; - printk_debug("i82801gx_sata: initializing...\n"); + printk(BIOS_DEBUG, "i82801gx_sata: initializing...\n"); if (config == NULL) { - printk_err("i82801gx_sata: error: device not in Config.lb!\n"); + printk(BIOS_ERR, "i82801gx_sata: error: device not in Config.lb!\n"); return; } @@ -46,7 +46,7 @@ static void sata_init(struct device *dev) pci_write_config16(dev, PCI_COMMAND, 0x0007); if (config->ide_legacy_combined) { - printk_debug("SATA controller in combined mode.\n"); + printk(BIOS_DEBUG, "SATA controller in combined mode.\n"); /* No AHCI: clear AHCI base */ pci_write_config32(dev, 0x24, 0x00000000); /* And without AHCI BAR no memory decoding */ @@ -80,7 +80,7 @@ static void sata_init(struct device *dev) /* SATA Initialization register */ pci_write_config32(dev, 0x94, 0x5a000180); } else if(config->sata_ahci) { - printk_debug("SATA controller in AHCI mode.\n"); + printk(BIOS_DEBUG, "SATA controller in AHCI mode.\n"); /* Allow both Legacy and Native mode */ pci_write_config8(dev, 0x09, 0x8f); @@ -112,7 +112,7 @@ static void sata_init(struct device *dev) /* SATA Initialization register */ pci_write_config32(dev, 0x94, 0x1a000180); } else { - printk_debug("SATA controller in plain mode.\n"); + printk(BIOS_DEBUG, "SATA controller in plain mode.\n"); /* Set Sata Controller Mode. No Mapping(?) */ pci_write_config8(dev, 0x90, 0x00); diff --git a/src/southbridge/intel/i82801gx/i82801gx_smbus.c b/src/southbridge/intel/i82801gx/i82801gx_smbus.c index 4306055d37..50c6d0f342 100644 --- a/src/southbridge/intel/i82801gx/i82801gx_smbus.c +++ b/src/southbridge/intel/i82801gx/i82801gx_smbus.c @@ -35,11 +35,11 @@ static void smbus_init(struct device *dev) u32 smb_base; smb_base = pci_read_config32(dev, SMB_BASE); - printk_debug("Initializing SMBus device:\n"); - printk_debug(" Old SMBUS Base Address: 0x%04x\n", smb_base); + printk(BIOS_DEBUG, "Initializing SMBus device:\n"); + printk(BIOS_DEBUG, " Old SMBUS Base Address: 0x%04x\n", smb_base); pci_write_config32(dev, SMB_BASE, 0x00000401); smb_base = pci_read_config32(dev, SMB_BASE); - printk_debug(" New SMBUS Base Address: 0x%04x\n", smb_base); + printk(BIOS_DEBUG, " New SMBUS Base Address: 0x%04x\n", smb_base); } static int lsmbus_read_byte(device_t dev, u8 address) diff --git a/src/southbridge/intel/i82801gx/i82801gx_smi.c b/src/southbridge/intel/i82801gx/i82801gx_smi.c index 0c70812412..3ba21b0dd1 100644 --- a/src/southbridge/intel/i82801gx/i82801gx_smi.c +++ b/src/southbridge/intel/i82801gx/i82801gx_smi.c @@ -63,16 +63,16 @@ static u16 reset_pm1_status(void) static void dump_pm1_status(u16 pm1_sts) { - printk_debug("PM1_STS: "); - if (pm1_sts & (1 << 15)) printk_debug("WAK "); - if (pm1_sts & (1 << 14)) printk_debug("PCIEXPWAK "); - if (pm1_sts & (1 << 11)) printk_debug("PRBTNOR "); - if (pm1_sts & (1 << 10)) printk_debug("RTC "); - if (pm1_sts & (1 << 8)) printk_debug("PWRBTN "); - if (pm1_sts & (1 << 5)) printk_debug("GBL "); - if (pm1_sts & (1 << 4)) printk_debug("BM "); - if (pm1_sts & (1 << 0)) printk_debug("TMROF "); - printk_debug("\n"); + printk(BIOS_DEBUG, "PM1_STS: "); + if (pm1_sts & (1 << 15)) printk(BIOS_DEBUG, "WAK "); + if (pm1_sts & (1 << 14)) printk(BIOS_DEBUG, "PCIEXPWAK "); + if (pm1_sts & (1 << 11)) printk(BIOS_DEBUG, "PRBTNOR "); + if (pm1_sts & (1 << 10)) printk(BIOS_DEBUG, "RTC "); + if (pm1_sts & (1 << 8)) printk(BIOS_DEBUG, "PWRBTN "); + if (pm1_sts & (1 << 5)) printk(BIOS_DEBUG, "GBL "); + if (pm1_sts & (1 << 4)) printk(BIOS_DEBUG, "BM "); + if (pm1_sts & (1 << 0)) printk(BIOS_DEBUG, "TMROF "); + printk(BIOS_DEBUG, "\n"); } /** @@ -92,28 +92,28 @@ static u32 reset_smi_status(void) static void dump_smi_status(u32 smi_sts) { - printk_debug("SMI_STS: "); - if (smi_sts & (1 << 26)) printk_debug("SPI "); - if (smi_sts & (1 << 25)) printk_debug("EL_SMI "); - if (smi_sts & (1 << 21)) printk_debug("MONITOR "); - if (smi_sts & (1 << 20)) printk_debug("PCI_EXP_SMI "); - if (smi_sts & (1 << 18)) printk_debug("INTEL_USB2 "); - if (smi_sts & (1 << 17)) printk_debug("LEGACY_USB2 "); - if (smi_sts & (1 << 16)) printk_debug("SMBUS_SMI "); - if (smi_sts & (1 << 15)) printk_debug("SERIRQ_SMI "); - if (smi_sts & (1 << 14)) printk_debug("PERIODIC "); - if (smi_sts & (1 << 13)) printk_debug("TCO "); - if (smi_sts & (1 << 12)) printk_debug("DEVMON "); - if (smi_sts & (1 << 11)) printk_debug("MCSMI "); - if (smi_sts & (1 << 10)) printk_debug("GPI "); - if (smi_sts & (1 << 9)) printk_debug("GPE0 "); - if (smi_sts & (1 << 8)) printk_debug("PM1 "); - if (smi_sts & (1 << 6)) printk_debug("SWSMI_TMR "); - if (smi_sts & (1 << 5)) printk_debug("APM "); - if (smi_sts & (1 << 4)) printk_debug("SLP_SMI "); - if (smi_sts & (1 << 3)) printk_debug("LEGACY_USB "); - if (smi_sts & (1 << 2)) printk_debug("BIOS "); - printk_debug("\n"); + printk(BIOS_DEBUG, "SMI_STS: "); + if (smi_sts & (1 << 26)) printk(BIOS_DEBUG, "SPI "); + if (smi_sts & (1 << 25)) printk(BIOS_DEBUG, "EL_SMI "); + if (smi_sts & (1 << 21)) printk(BIOS_DEBUG, "MONITOR "); + if (smi_sts & (1 << 20)) printk(BIOS_DEBUG, "PCI_EXP_SMI "); + if (smi_sts & (1 << 18)) printk(BIOS_DEBUG, "INTEL_USB2 "); + if (smi_sts & (1 << 17)) printk(BIOS_DEBUG, "LEGACY_USB2 "); + if (smi_sts & (1 << 16)) printk(BIOS_DEBUG, "SMBUS_SMI "); + if (smi_sts & (1 << 15)) printk(BIOS_DEBUG, "SERIRQ_SMI "); + if (smi_sts & (1 << 14)) printk(BIOS_DEBUG, "PERIODIC "); + if (smi_sts & (1 << 13)) printk(BIOS_DEBUG, "TCO "); + if (smi_sts & (1 << 12)) printk(BIOS_DEBUG, "DEVMON "); + if (smi_sts & (1 << 11)) printk(BIOS_DEBUG, "MCSMI "); + if (smi_sts & (1 << 10)) printk(BIOS_DEBUG, "GPI "); + if (smi_sts & (1 << 9)) printk(BIOS_DEBUG, "GPE0 "); + if (smi_sts & (1 << 8)) printk(BIOS_DEBUG, "PM1 "); + if (smi_sts & (1 << 6)) printk(BIOS_DEBUG, "SWSMI_TMR "); + if (smi_sts & (1 << 5)) printk(BIOS_DEBUG, "APM "); + if (smi_sts & (1 << 4)) printk(BIOS_DEBUG, "SLP_SMI "); + if (smi_sts & (1 << 3)) printk(BIOS_DEBUG, "LEGACY_USB "); + if (smi_sts & (1 << 2)) printk(BIOS_DEBUG, "BIOS "); + printk(BIOS_DEBUG, "\n"); } @@ -135,25 +135,25 @@ static u32 reset_gpe0_status(void) static void dump_gpe0_status(u32 gpe0_sts) { int i; - printk_debug("GPE0_STS: "); + printk(BIOS_DEBUG, "GPE0_STS: "); for (i=31; i<= 16; i--) { - if (gpe0_sts & (1 << i)) printk_debug("GPIO%d ", (i-16)); + if (gpe0_sts & (1 << i)) printk(BIOS_DEBUG, "GPIO%d ", (i-16)); } - if (gpe0_sts & (1 << 14)) printk_debug("USB4 "); - if (gpe0_sts & (1 << 13)) printk_debug("PME_B0 "); - if (gpe0_sts & (1 << 12)) printk_debug("USB3 "); - if (gpe0_sts & (1 << 11)) printk_debug("PME "); - if (gpe0_sts & (1 << 10)) printk_debug("EL_SCI/BATLOW "); - if (gpe0_sts & (1 << 9)) printk_debug("PCI_EXP "); - if (gpe0_sts & (1 << 8)) printk_debug("RI "); - if (gpe0_sts & (1 << 7)) printk_debug("SMB_WAK "); - if (gpe0_sts & (1 << 6)) printk_debug("TCO_SCI "); - if (gpe0_sts & (1 << 5)) printk_debug("AC97 "); - if (gpe0_sts & (1 << 4)) printk_debug("USB2 "); - if (gpe0_sts & (1 << 3)) printk_debug("USB1 "); - if (gpe0_sts & (1 << 2)) printk_debug("HOT_PLUG "); - if (gpe0_sts & (1 << 0)) printk_debug("THRM "); - printk_debug("\n"); + if (gpe0_sts & (1 << 14)) printk(BIOS_DEBUG, "USB4 "); + if (gpe0_sts & (1 << 13)) printk(BIOS_DEBUG, "PME_B0 "); + if (gpe0_sts & (1 << 12)) printk(BIOS_DEBUG, "USB3 "); + if (gpe0_sts & (1 << 11)) printk(BIOS_DEBUG, "PME "); + if (gpe0_sts & (1 << 10)) printk(BIOS_DEBUG, "EL_SCI/BATLOW "); + if (gpe0_sts & (1 << 9)) printk(BIOS_DEBUG, "PCI_EXP "); + if (gpe0_sts & (1 << 8)) printk(BIOS_DEBUG, "RI "); + if (gpe0_sts & (1 << 7)) printk(BIOS_DEBUG, "SMB_WAK "); + if (gpe0_sts & (1 << 6)) printk(BIOS_DEBUG, "TCO_SCI "); + if (gpe0_sts & (1 << 5)) printk(BIOS_DEBUG, "AC97 "); + if (gpe0_sts & (1 << 4)) printk(BIOS_DEBUG, "USB2 "); + if (gpe0_sts & (1 << 3)) printk(BIOS_DEBUG, "USB1 "); + if (gpe0_sts & (1 << 2)) printk(BIOS_DEBUG, "HOT_PLUG "); + if (gpe0_sts & (1 << 0)) printk(BIOS_DEBUG, "THRM "); + printk(BIOS_DEBUG, "\n"); } @@ -175,11 +175,11 @@ static u16 reset_alt_gp_smi_status(void) static void dump_alt_gp_smi_status(u16 alt_gp_smi_sts) { int i; - printk_debug("ALT_GP_SMI_STS: "); + printk(BIOS_DEBUG, "ALT_GP_SMI_STS: "); for (i=15; i<= 0; i--) { - if (alt_gp_smi_sts & (1 << i)) printk_debug("GPI%d ", (i-16)); + if (alt_gp_smi_sts & (1 << i)) printk(BIOS_DEBUG, "GPI%d ", (i-16)); } - printk_debug("\n"); + printk(BIOS_DEBUG, "\n"); } @@ -205,21 +205,21 @@ static u32 reset_tco_status(void) static void dump_tco_status(u32 tco_sts) { - printk_debug("TCO_STS: "); - if (tco_sts & (1 << 20)) printk_debug("SMLINK_SLV "); - if (tco_sts & (1 << 18)) printk_debug("BOOT "); - if (tco_sts & (1 << 17)) printk_debug("SECOND_TO "); - if (tco_sts & (1 << 16)) printk_debug("INTRD_DET "); - if (tco_sts & (1 << 12)) printk_debug("DMISERR "); - if (tco_sts & (1 << 10)) printk_debug("DMISMI "); - if (tco_sts & (1 << 9)) printk_debug("DMISCI "); - if (tco_sts & (1 << 8)) printk_debug("BIOSWR "); - if (tco_sts & (1 << 7)) printk_debug("NEWCENTURY "); - if (tco_sts & (1 << 3)) printk_debug("TIMEOUT "); - if (tco_sts & (1 << 2)) printk_debug("TCO_INT "); - if (tco_sts & (1 << 1)) printk_debug("SW_TCO "); - if (tco_sts & (1 << 0)) printk_debug("NMI2SMI "); - printk_debug("\n"); + printk(BIOS_DEBUG, "TCO_STS: "); + if (tco_sts & (1 << 20)) printk(BIOS_DEBUG, "SMLINK_SLV "); + if (tco_sts & (1 << 18)) printk(BIOS_DEBUG, "BOOT "); + if (tco_sts & (1 << 17)) printk(BIOS_DEBUG, "SECOND_TO "); + if (tco_sts & (1 << 16)) printk(BIOS_DEBUG, "INTRD_DET "); + if (tco_sts & (1 << 12)) printk(BIOS_DEBUG, "DMISERR "); + if (tco_sts & (1 << 10)) printk(BIOS_DEBUG, "DMISMI "); + if (tco_sts & (1 << 9)) printk(BIOS_DEBUG, "DMISCI "); + if (tco_sts & (1 << 8)) printk(BIOS_DEBUG, "BIOSWR "); + if (tco_sts & (1 << 7)) printk(BIOS_DEBUG, "NEWCENTURY "); + if (tco_sts & (1 << 3)) printk(BIOS_DEBUG, "TIMEOUT "); + if (tco_sts & (1 << 2)) printk(BIOS_DEBUG, "TCO_INT "); + if (tco_sts & (1 << 1)) printk(BIOS_DEBUG, "SW_TCO "); + if (tco_sts & (1 << 0)) printk(BIOS_DEBUG, "NMI2SMI "); + printk(BIOS_DEBUG, "\n"); } @@ -243,14 +243,14 @@ static void smm_relocate(void) u32 smi_en; u16 pm1_en; - printk_debug("Initializing SMM handler..."); + printk(BIOS_DEBUG, "Initializing SMM handler..."); pmbase = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f, 0)), 0x40) & 0xfffc; - printk_spew(" ... pmbase = 0x%04x\n", pmbase); + printk(BIOS_SPEW, " ... pmbase = 0x%04x\n", pmbase); smi_en = inl(pmbase + SMI_EN); if (smi_en & APMC_EN) { - printk_info("SMI# handler already enabled?\n"); + printk(BIOS_INFO, "SMI# handler already enabled?\n"); return; } @@ -258,7 +258,7 @@ static void smm_relocate(void) memcpy((void *)0x38000, &smm_relocation_start, &smm_relocation_end - &smm_relocation_start); - printk_debug("\n"); + printk(BIOS_DEBUG, "\n"); dump_smi_status(reset_smi_status()); dump_pm1_status(reset_pm1_status()); dump_gpe0_status(reset_gpe0_status()); @@ -314,7 +314,7 @@ static void smm_relocate(void) */ /* raise an SMI interrupt */ - printk_spew(" ... raise SMI#\n"); + printk(BIOS_SPEW, " ... raise SMI#\n"); outb(0x00, 0xb2); } @@ -349,7 +349,7 @@ void smm_lock(void) * After running this function, only a full reset can * make the SMM registers writable again. */ - printk_debug("Locking SMM.\n"); + printk(BIOS_DEBUG, "Locking SMM.\n"); pci_write_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), SMRAM, D_LCK | G_SMRAME | C_BASE_SEG); } diff --git a/src/southbridge/intel/i82801gx/i82801gx_smihandler.c b/src/southbridge/intel/i82801gx/i82801gx_smihandler.c index 9cd0370cdc..b478dbaa90 100644 --- a/src/southbridge/intel/i82801gx/i82801gx_smihandler.c +++ b/src/southbridge/intel/i82801gx/i82801gx_smihandler.c @@ -76,18 +76,18 @@ static u16 reset_pm1_status(void) static void dump_pm1_status(u16 pm1_sts) { - printk_spew("PM1_STS: "); - if (pm1_sts & (1 << 15)) printk_spew("WAK "); - if (pm1_sts & (1 << 14)) printk_spew("PCIEXPWAK "); - if (pm1_sts & (1 << 11)) printk_spew("PRBTNOR "); - if (pm1_sts & (1 << 10)) printk_spew("RTC "); - if (pm1_sts & (1 << 8)) printk_spew("PWRBTN "); - if (pm1_sts & (1 << 5)) printk_spew("GBL "); - if (pm1_sts & (1 << 4)) printk_spew("BM "); - if (pm1_sts & (1 << 0)) printk_spew("TMROF "); - printk_spew("\n"); + printk(BIOS_SPEW, "PM1_STS: "); + if (pm1_sts & (1 << 15)) printk(BIOS_SPEW, "WAK "); + if (pm1_sts & (1 << 14)) printk(BIOS_SPEW, "PCIEXPWAK "); + if (pm1_sts & (1 << 11)) printk(BIOS_SPEW, "PRBTNOR "); + if (pm1_sts & (1 << 10)) printk(BIOS_SPEW, "RTC "); + if (pm1_sts & (1 << 8)) printk(BIOS_SPEW, "PWRBTN "); + if (pm1_sts & (1 << 5)) printk(BIOS_SPEW, "GBL "); + if (pm1_sts & (1 << 4)) printk(BIOS_SPEW, "BM "); + if (pm1_sts & (1 << 0)) printk(BIOS_SPEW, "TMROF "); + printk(BIOS_SPEW, "\n"); int reg16 = inw(pmbase + PM1_EN); - printk_spew("PM1_EN: %x\n", reg16); + printk(BIOS_SPEW, "PM1_EN: %x\n", reg16); } /** @@ -107,28 +107,28 @@ static u32 reset_smi_status(void) static void dump_smi_status(u32 smi_sts) { - printk_debug("SMI_STS: "); - if (smi_sts & (1 << 26)) printk_debug("SPI "); - if (smi_sts & (1 << 25)) printk_debug("EL_SMI "); - if (smi_sts & (1 << 21)) printk_debug("MONITOR "); - if (smi_sts & (1 << 20)) printk_debug("PCI_EXP_SMI "); - if (smi_sts & (1 << 18)) printk_debug("INTEL_USB2 "); - if (smi_sts & (1 << 17)) printk_debug("LEGACY_USB2 "); - if (smi_sts & (1 << 16)) printk_debug("SMBUS_SMI "); - if (smi_sts & (1 << 15)) printk_debug("SERIRQ_SMI "); - if (smi_sts & (1 << 14)) printk_debug("PERIODIC "); - if (smi_sts & (1 << 13)) printk_debug("TCO "); - if (smi_sts & (1 << 12)) printk_debug("DEVMON "); - if (smi_sts & (1 << 11)) printk_debug("MCSMI "); - if (smi_sts & (1 << 10)) printk_debug("GPI "); - if (smi_sts & (1 << 9)) printk_debug("GPE0 "); - if (smi_sts & (1 << 8)) printk_debug("PM1 "); - if (smi_sts & (1 << 6)) printk_debug("SWSMI_TMR "); - if (smi_sts & (1 << 5)) printk_debug("APM "); - if (smi_sts & (1 << 4)) printk_debug("SLP_SMI "); - if (smi_sts & (1 << 3)) printk_debug("LEGACY_USB "); - if (smi_sts & (1 << 2)) printk_debug("BIOS "); - printk_debug("\n"); + printk(BIOS_DEBUG, "SMI_STS: "); + if (smi_sts & (1 << 26)) printk(BIOS_DEBUG, "SPI "); + if (smi_sts & (1 << 25)) printk(BIOS_DEBUG, "EL_SMI "); + if (smi_sts & (1 << 21)) printk(BIOS_DEBUG, "MONITOR "); + if (smi_sts & (1 << 20)) printk(BIOS_DEBUG, "PCI_EXP_SMI "); + if (smi_sts & (1 << 18)) printk(BIOS_DEBUG, "INTEL_USB2 "); + if (smi_sts & (1 << 17)) printk(BIOS_DEBUG, "LEGACY_USB2 "); + if (smi_sts & (1 << 16)) printk(BIOS_DEBUG, "SMBUS_SMI "); + if (smi_sts & (1 << 15)) printk(BIOS_DEBUG, "SERIRQ_SMI "); + if (smi_sts & (1 << 14)) printk(BIOS_DEBUG, "PERIODIC "); + if (smi_sts & (1 << 13)) printk(BIOS_DEBUG, "TCO "); + if (smi_sts & (1 << 12)) printk(BIOS_DEBUG, "DEVMON "); + if (smi_sts & (1 << 11)) printk(BIOS_DEBUG, "MCSMI "); + if (smi_sts & (1 << 10)) printk(BIOS_DEBUG, "GPI "); + if (smi_sts & (1 << 9)) printk(BIOS_DEBUG, "GPE0 "); + if (smi_sts & (1 << 8)) printk(BIOS_DEBUG, "PM1 "); + if (smi_sts & (1 << 6)) printk(BIOS_DEBUG, "SWSMI_TMR "); + if (smi_sts & (1 << 5)) printk(BIOS_DEBUG, "APM "); + if (smi_sts & (1 << 4)) printk(BIOS_DEBUG, "SLP_SMI "); + if (smi_sts & (1 << 3)) printk(BIOS_DEBUG, "LEGACY_USB "); + if (smi_sts & (1 << 2)) printk(BIOS_DEBUG, "BIOS "); + printk(BIOS_DEBUG, "\n"); } @@ -150,25 +150,25 @@ static u32 reset_gpe0_status(void) static void dump_gpe0_status(u32 gpe0_sts) { int i; - printk_debug("GPE0_STS: "); + printk(BIOS_DEBUG, "GPE0_STS: "); for (i=31; i<= 16; i--) { - if (gpe0_sts & (1 << i)) printk_debug("GPIO%d ", (i-16)); + if (gpe0_sts & (1 << i)) printk(BIOS_DEBUG, "GPIO%d ", (i-16)); } - if (gpe0_sts & (1 << 14)) printk_debug("USB4 "); - if (gpe0_sts & (1 << 13)) printk_debug("PME_B0 "); - if (gpe0_sts & (1 << 12)) printk_debug("USB3 "); - if (gpe0_sts & (1 << 11)) printk_debug("PME "); - if (gpe0_sts & (1 << 10)) printk_debug("EL_SCI/BATLOW "); - if (gpe0_sts & (1 << 9)) printk_debug("PCI_EXP "); - if (gpe0_sts & (1 << 8)) printk_debug("RI "); - if (gpe0_sts & (1 << 7)) printk_debug("SMB_WAK "); - if (gpe0_sts & (1 << 6)) printk_debug("TCO_SCI "); - if (gpe0_sts & (1 << 5)) printk_debug("AC97 "); - if (gpe0_sts & (1 << 4)) printk_debug("USB2 "); - if (gpe0_sts & (1 << 3)) printk_debug("USB1 "); - if (gpe0_sts & (1 << 2)) printk_debug("HOT_PLUG "); - if (gpe0_sts & (1 << 0)) printk_debug("THRM "); - printk_debug("\n"); + if (gpe0_sts & (1 << 14)) printk(BIOS_DEBUG, "USB4 "); + if (gpe0_sts & (1 << 13)) printk(BIOS_DEBUG, "PME_B0 "); + if (gpe0_sts & (1 << 12)) printk(BIOS_DEBUG, "USB3 "); + if (gpe0_sts & (1 << 11)) printk(BIOS_DEBUG, "PME "); + if (gpe0_sts & (1 << 10)) printk(BIOS_DEBUG, "EL_SCI/BATLOW "); + if (gpe0_sts & (1 << 9)) printk(BIOS_DEBUG, "PCI_EXP "); + if (gpe0_sts & (1 << 8)) printk(BIOS_DEBUG, "RI "); + if (gpe0_sts & (1 << 7)) printk(BIOS_DEBUG, "SMB_WAK "); + if (gpe0_sts & (1 << 6)) printk(BIOS_DEBUG, "TCO_SCI "); + if (gpe0_sts & (1 << 5)) printk(BIOS_DEBUG, "AC97 "); + if (gpe0_sts & (1 << 4)) printk(BIOS_DEBUG, "USB2 "); + if (gpe0_sts & (1 << 3)) printk(BIOS_DEBUG, "USB1 "); + if (gpe0_sts & (1 << 2)) printk(BIOS_DEBUG, "HOT_PLUG "); + if (gpe0_sts & (1 << 0)) printk(BIOS_DEBUG, "THRM "); + printk(BIOS_DEBUG, "\n"); } @@ -193,21 +193,21 @@ static u32 reset_tco_status(void) static void dump_tco_status(u32 tco_sts) { - printk_debug("TCO_STS: "); - if (tco_sts & (1 << 20)) printk_debug("SMLINK_SLV "); - if (tco_sts & (1 << 18)) printk_debug("BOOT "); - if (tco_sts & (1 << 17)) printk_debug("SECOND_TO "); - if (tco_sts & (1 << 16)) printk_debug("INTRD_DET "); - if (tco_sts & (1 << 12)) printk_debug("DMISERR "); - if (tco_sts & (1 << 10)) printk_debug("DMISMI "); - if (tco_sts & (1 << 9)) printk_debug("DMISCI "); - if (tco_sts & (1 << 8)) printk_debug("BIOSWR "); - if (tco_sts & (1 << 7)) printk_debug("NEWCENTURY "); - if (tco_sts & (1 << 3)) printk_debug("TIMEOUT "); - if (tco_sts & (1 << 2)) printk_debug("TCO_INT "); - if (tco_sts & (1 << 1)) printk_debug("SW_TCO "); - if (tco_sts & (1 << 0)) printk_debug("NMI2SMI "); - printk_debug("\n"); + printk(BIOS_DEBUG, "TCO_STS: "); + if (tco_sts & (1 << 20)) printk(BIOS_DEBUG, "SMLINK_SLV "); + if (tco_sts & (1 << 18)) printk(BIOS_DEBUG, "BOOT "); + if (tco_sts & (1 << 17)) printk(BIOS_DEBUG, "SECOND_TO "); + if (tco_sts & (1 << 16)) printk(BIOS_DEBUG, "INTRD_DET "); + if (tco_sts & (1 << 12)) printk(BIOS_DEBUG, "DMISERR "); + if (tco_sts & (1 << 10)) printk(BIOS_DEBUG, "DMISMI "); + if (tco_sts & (1 << 9)) printk(BIOS_DEBUG, "DMISCI "); + if (tco_sts & (1 << 8)) printk(BIOS_DEBUG, "BIOSWR "); + if (tco_sts & (1 << 7)) printk(BIOS_DEBUG, "NEWCENTURY "); + if (tco_sts & (1 << 3)) printk(BIOS_DEBUG, "TIMEOUT "); + if (tco_sts & (1 << 2)) printk(BIOS_DEBUG, "TCO_INT "); + if (tco_sts & (1 << 1)) printk(BIOS_DEBUG, "SW_TCO "); + if (tco_sts & (1 << 0)) printk(BIOS_DEBUG, "NMI2SMI "); + printk(BIOS_DEBUG, "\n"); } /* We are using PCIe accesses for now @@ -220,7 +220,7 @@ int southbridge_io_trap_handler(int smif) { switch (smif) { case 0x32: - printk_debug("OS Init\n"); + printk(BIOS_DEBUG, "OS Init\n"); /* gnvs->smif: * On success, the IO Trap Handler returns 0 * On failure, the IO Trap Handler returns a value != 0 @@ -299,23 +299,23 @@ static void southbridge_smi_sleep(unsigned int node, smm_state_save_area_t *stat /* Figure out SLP_TYP */ reg32 = inl(pmbase + PM1_CNT); - printk_spew("SMI#: SLP = 0x%08x\n", reg32); + printk(BIOS_SPEW, "SMI#: SLP = 0x%08x\n", reg32); slp_typ = (reg32 >> 10) & 7; /* Next, do the deed. */ switch (slp_typ) { - case 0: printk_debug("SMI#: Entering S0 (On)\n"); break; - case 1: printk_debug("SMI#: Entering S1 (Assert STPCLK#)\n"); break; + case 0: printk(BIOS_DEBUG, "SMI#: Entering S0 (On)\n"); break; + case 1: printk(BIOS_DEBUG, "SMI#: Entering S1 (Assert STPCLK#)\n"); break; case 5: - printk_debug("SMI#: Entering S3 (Suspend-To-RAM)\n"); + printk(BIOS_DEBUG, "SMI#: Entering S3 (Suspend-To-RAM)\n"); /* Invalidate the cache before going to S3 */ wbinvd(); break; - case 6: printk_debug("SMI#: Entering S4 (Suspend-To-Disk)\n"); break; + case 6: printk(BIOS_DEBUG, "SMI#: Entering S4 (Suspend-To-Disk)\n"); break; case 7: - printk_debug("SMI#: Entering S5 (Soft Power off)\n"); + printk(BIOS_DEBUG, "SMI#: Entering S5 (Soft Power off)\n"); outl(0, pmbase + GPE0_EN); @@ -333,7 +333,7 @@ static void southbridge_smi_sleep(unsigned int node, smm_state_save_area_t *stat /* also iterates over all bridges on bus 0 */ busmaster_disable_on_bus(0); break; - default: printk_debug("SMI#: ERROR: SLP_TYP reserved\n"); break; + default: printk(BIOS_DEBUG, "SMI#: ERROR: SLP_TYP reserved\n"); break; } /* Write back to the SLP register to cause the originally intended @@ -368,40 +368,40 @@ static void southbridge_smi_apmc(unsigned int node, smm_state_save_area_t *state * some kind of race condition in Linux * and causes a kernel oops */ - printk_debug("C-state control\n"); + printk(BIOS_DEBUG, "C-state control\n"); break; case PST_CONTROL: /* Calling this function seems to cause * some kind of race condition in Linux * and causes a kernel oops */ - printk_debug("P-state control\n"); + printk(BIOS_DEBUG, "P-state control\n"); break; case ACPI_DISABLE: pmctrl = inl(pmbase + PM1_CNT); pmctrl &= ~SCI_EN; outl(pmctrl, pmbase + PM1_CNT); - printk_debug("SMI#: ACPI disabled.\n"); + printk(BIOS_DEBUG, "SMI#: ACPI disabled.\n"); break; case ACPI_ENABLE: pmctrl = inl(pmbase + PM1_CNT); pmctrl |= SCI_EN; outl(pmctrl, pmbase + PM1_CNT); - printk_debug("SMI#: ACPI enabled.\n"); + printk(BIOS_DEBUG, "SMI#: ACPI enabled.\n"); break; case GNVS_UPDATE: if (smm_initialized) { - printk_debug("SMI#: SMM structures already initialized!\n"); + printk(BIOS_DEBUG, "SMI#: SMM structures already initialized!\n"); return; } gnvs = *(global_nvs_t **)0x500; tcg = *(void **)0x504; smi1 = *(void **)0x508; smm_initialized = 1; - printk_debug("SMI#: Setting up structures to %p, %p, %p\n", gnvs, tcg, smi1); + printk(BIOS_DEBUG, "SMI#: Setting up structures to %p, %p, %p\n", gnvs, tcg, smi1); break; default: - printk_debug("SMI#: Unknown function APM_CNT=%02x\n", reg8); + printk(BIOS_DEBUG, "SMI#: Unknown function APM_CNT=%02x\n", reg8); } } @@ -445,7 +445,7 @@ static void southbridge_smi_gpi(unsigned int node, smm_state_save_area_t *state_ mainboard_smi_gpi(reg16); } else { if (reg16) - printk_debug("GPI (mask %04x)\n",reg16); + printk(BIOS_DEBUG, "GPI (mask %04x)\n",reg16); } } @@ -459,7 +459,7 @@ static void southbridge_smi_mc(unsigned int node, smm_state_save_area_t *state_s if ((reg32 & MCSMI_EN) == 0) return; - printk_debug("Microcontroller SMI.\n"); + printk(BIOS_DEBUG, "Microcontroller SMI.\n"); } @@ -490,12 +490,12 @@ static void southbridge_smi_tco(unsigned int node, smm_state_save_area_t *state_ * resolute answer would be to power down the * box. */ - printk_debug("Switching back to RO\n"); + printk(BIOS_DEBUG, "Switching back to RO\n"); pcie_write_config32(PCI_DEV(0, 0x1f, 0), 0xdc, (bios_cntl & ~1)); } /* No else for now? */ } else if (tco_sts & (1 << 3)) { /* TIMEOUT */ /* Handle TCO timeout */ - printk_debug("TCO Timeout.\n"); + printk(BIOS_DEBUG, "TCO Timeout.\n"); } else if (!tco_sts) { dump_tco_status(tco_sts); } @@ -511,7 +511,7 @@ static void southbridge_smi_periodic(unsigned int node, smm_state_save_area_t *s if ((reg32 & PERIODIC_EN) == 0) return; - printk_debug("Periodic SMI.\n"); + printk(BIOS_DEBUG, "Periodic SMI.\n"); } static void southbridge_smi_monitor(unsigned int node, smm_state_save_area_t *state_save) @@ -544,7 +544,7 @@ static void southbridge_smi_monitor(unsigned int node, smm_state_save_area_t *st /* IOTRAP(0) SMIC */ if (IOTRAP(0)) { if (!(trap_cycle & (1 << 24))) { // It's a write - printk_debug("SMI1 command\n"); + printk(BIOS_DEBUG, "SMI1 command\n"); data = RCBA32(0x1e18); data &= mask; // if (smi1) @@ -554,16 +554,16 @@ static void southbridge_smi_monitor(unsigned int node, smm_state_save_area_t *st // Fall through to debug } - printk_debug(" trapped io address = 0x%x\n", trap_cycle & 0xfffc); - for (i=0; i < 4; i++) if(IOTRAP(i)) printk_debug(" TRAPÂ = %d\n", i); - printk_debug(" AHBE = %x\n", (trap_cycle >> 16) & 0xf); - printk_debug(" MASK = 0x%08x\n", mask); - printk_debug(" read/write: %s\n", (trap_cycle & (1 << 24)) ? "read" : "write"); + printk(BIOS_DEBUG, " trapped io address = 0x%x\n", trap_cycle & 0xfffc); + for (i=0; i < 4; i++) if(IOTRAP(i)) printk(BIOS_DEBUG, " TRAPÂ = %d\n", i); + printk(BIOS_DEBUG, " AHBE = %x\n", (trap_cycle >> 16) & 0xf); + printk(BIOS_DEBUG, " MASK = 0x%08x\n", mask); + printk(BIOS_DEBUG, " read/write: %s\n", (trap_cycle & (1 << 24)) ? "read" : "write"); if (!(trap_cycle & (1 << 24))) { /* Write Cycle */ data = RCBA32(0x1e18); - printk_debug(" iotrap written data = 0x%08x\n", data); + printk(BIOS_DEBUG, " iotrap written data = 0x%08x\n", data); } #undef IOTRAP } @@ -635,7 +635,7 @@ void southbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_sav if (southbridge_smi[i]) southbridge_smi[i](node, state_save); else { - printk_debug("SMI_STS[%d] occured, but no " + printk(BIOS_DEBUG, "SMI_STS[%d] occured, but no " "handler available.\n", i); dump = 1; } diff --git a/src/southbridge/intel/i82801gx/i82801gx_usb.c b/src/southbridge/intel/i82801gx/i82801gx_usb.c index 2803f9cdef..00fddf7c65 100644 --- a/src/southbridge/intel/i82801gx/i82801gx_usb.c +++ b/src/southbridge/intel/i82801gx/i82801gx_usb.c @@ -30,7 +30,7 @@ static void usb_init(struct device *dev) u8 reg8; /* USB Specification says the device must be Bus Master */ - printk_debug("UHCI: Setting up controller.. "); + printk(BIOS_DEBUG, "UHCI: Setting up controller.. "); reg32 = pci_read_config32(dev, PCI_COMMAND); pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER); @@ -43,7 +43,7 @@ static void usb_init(struct device *dev) reg8 |= (1 << 0); pci_write_config8(dev, 0xca, reg8); - printk_debug("done.\n"); + printk(BIOS_DEBUG, "done.\n"); } static void usb_set_subsystem(device_t dev, unsigned vendor, unsigned device) diff --git a/src/southbridge/intel/i82801gx/i82801gx_usb_debug.c b/src/southbridge/intel/i82801gx/i82801gx_usb_debug.c index 829ae6b819..ead7bdca7f 100644 --- a/src/southbridge/intel/i82801gx/i82801gx_usb_debug.c +++ b/src/southbridge/intel/i82801gx/i82801gx_usb_debug.c @@ -30,7 +30,7 @@ void set_debug_port(unsigned port) { u32 dbgctl; - printk_debug("Enabling OWNER_CNT\n"); + printk(BIOS_DEBUG, "Enabling OWNER_CNT\n"); dbgctl = read32(EHCI_BAR + EHCI_DEBUG_OFFSET); dbgctl |= (1 << 30); write32(EHCI_BAR + EHCI_DEBUG_OFFSET, dbgctl); diff --git a/src/southbridge/intel/i82801gx/i82801gx_usb_ehci.c b/src/southbridge/intel/i82801gx/i82801gx_usb_ehci.c index 3d61cae9b6..1bc5fcaecb 100644 --- a/src/southbridge/intel/i82801gx/i82801gx_usb_ehci.c +++ b/src/southbridge/intel/i82801gx/i82801gx_usb_ehci.c @@ -35,7 +35,7 @@ static void usb_ehci_init(struct device *dev) u32 reg32; u8 reg8; - printk_debug("EHCI: Setting up controller.. "); + printk(BIOS_DEBUG, "EHCI: Setting up controller.. "); reg32 = pci_read_config32(dev, PCI_COMMAND); reg32 |= PCI_COMMAND_MASTER; reg32 |= PCI_COMMAND_SERR; @@ -61,7 +61,7 @@ static void usb_ehci_init(struct device *dev) reg8 |= (1 << 4); pci_write_config8(dev, 0x84, reg8); - printk_debug("done.\n"); + printk(BIOS_DEBUG, "done.\n"); } static void usb_ehci_set_subsystem(device_t dev, unsigned vendor, unsigned device) diff --git a/src/southbridge/intel/i82801gx/i82801gx_watchdog.c b/src/southbridge/intel/i82801gx/i82801gx_watchdog.c index 38350d7ef2..436a9227cd 100644 --- a/src/southbridge/intel/i82801gx/i82801gx_watchdog.c +++ b/src/southbridge/intel/i82801gx/i82801gx_watchdog.c @@ -49,5 +49,5 @@ void watchdog_off(void) outw(0x0008, base + 0x04); outw(0x0002, base + 0x06); - printk_debug("ICH7 watchdog disabled\r\n"); + printk(BIOS_DEBUG, "ICH7 watchdog disabled\r\n"); } diff --git a/src/southbridge/intel/i82870/p64h2_ioapic.c b/src/southbridge/intel/i82870/p64h2_ioapic.c index 0fa74ffcf3..d90fede890 100644 --- a/src/southbridge/intel/i82870/p64h2_ioapic.c +++ b/src/southbridge/intel/i82870/p64h2_ioapic.c @@ -62,7 +62,7 @@ static void p64h2_ioapic_init(device_t dev) pIndexRegister = (volatile uint32_t*) memoryBase; pWindowRegister = (volatile uint32_t*)(memoryBase + 0x10); - printk_debug("IOAPIC %d at %02x:%02x.%01x MBAR = %x DataAddr = %x\n", + printk(BIOS_DEBUG, "IOAPIC %d at %02x:%02x.%01x MBAR = %x DataAddr = %x\n", apic_id, dev->bus->secondary, PCI_SLOT(dev->path.pci.devfn), PCI_FUNC(dev->path.pci.devfn), pIndexRegister, pWindowRegister); diff --git a/src/southbridge/intel/pxhd/pxhd_bridge.c b/src/southbridge/intel/pxhd/pxhd_bridge.c index 0766b22e7b..0a50e5a994 100644 --- a/src/southbridge/intel/pxhd/pxhd_bridge.c +++ b/src/southbridge/intel/pxhd/pxhd_bridge.c @@ -22,7 +22,7 @@ static void pxhd_enable(device_t dev) } bridge = dev_find_slot(dev->bus->secondary, dev->path.pci.devfn & ~1); if (!bridge) { - printk_err("Cannot find bridge for ioapic: %s\n", + printk(BIOS_ERR, "Cannot find bridge for ioapic: %s\n", dev_path(dev)); return; } @@ -48,7 +48,7 @@ static unsigned int pxhd_scan_bridge(device_t dev, unsigned int max) if(bus_100Mhz) { uint16_t word; - printk_debug("setting pxhd bus to 100 Mhz\n"); + printk(BIOS_DEBUG, "setting pxhd bus to 100 Mhz\n"); /* set to pcix 100 mhz */ word = pci_read_config16(dev, 0x40); word &= ~(3 << 14); diff --git a/src/southbridge/nvidia/ck804/ck804_fadt.c b/src/southbridge/nvidia/ck804/ck804_fadt.c index 1bfc22d915..205f1f0550 100644 --- a/src/southbridge/nvidia/ck804/ck804_fadt.c +++ b/src/southbridge/nvidia/ck804/ck804_fadt.c @@ -13,7 +13,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) { acpi_header_t *header = &(fadt->header); - printk_debug("pm_base: 0x%04x\n", pm_base); + printk(BIOS_DEBUG, "pm_base: 0x%04x\n", pm_base); /* Prepare the header */ memset((void *)fadt, 0, sizeof(acpi_fadt_t)); diff --git a/src/southbridge/nvidia/ck804/ck804_ide.c b/src/southbridge/nvidia/ck804/ck804_ide.c index df4659c228..f46a057ef7 100644 --- a/src/southbridge/nvidia/ck804/ck804_ide.c +++ b/src/southbridge/nvidia/ck804/ck804_ide.c @@ -25,12 +25,12 @@ static void ide_init(struct device *dev) if (conf->ide1_enable) { /* Enable secondary IDE interface. */ word |= (1 << 0); - printk_debug("IDE1 \t"); + printk(BIOS_DEBUG, "IDE1 \t"); } if (conf->ide0_enable) { /* Enable primary IDE interface. */ word |= (1 << 1); - printk_debug("IDE0\n"); + printk(BIOS_DEBUG, "IDE0\n"); } word |= (1 << 12); diff --git a/src/southbridge/nvidia/ck804/ck804_lpc.c b/src/southbridge/nvidia/ck804/ck804_lpc.c index 2b840fcbdd..d68a5b1077 100644 --- a/src/southbridge/nvidia/ck804/ck804_lpc.c +++ b/src/southbridge/nvidia/ck804/ck804_lpc.c @@ -95,7 +95,7 @@ static void enable_hpet(struct device *dev) pci_write_config32(dev, 0x44, 0xfed00001); hpet_address = pci_read_config32(dev, 0x44) & 0xfffffffe; - printk_debug("Enabling HPET @0x%lx\n", hpet_address); + printk(BIOS_DEBUG, "Enabling HPET @0x%lx\n", hpet_address); } unsigned pm_base=0; @@ -108,7 +108,7 @@ static void lpc_init(device_t dev) lpc_common_init(dev); pm_base = pci_read_config32(dev, 0x60) & 0xff00; - printk_info("%s: pm_base = %x \n", __func__, pm_base); + printk(BIOS_INFO, "%s: pm_base = %x \n", __func__, pm_base); #if CK804_CHIP_REV==1 if (dev->bus->secondary != 1) @@ -129,7 +129,7 @@ static void lpc_init(device_t dev) if (!on) byte |= 0x40; pci_write_config8(dev, PREVIOUS_POWER_STATE, byte); - printk_info("set power %s after power fail\n", on ? "on" : "off"); + printk(BIOS_INFO, "set power %s after power fail\n", on ? "on" : "off"); /* Throttle the CPU speed down for testing. */ on = SLOW_CPU_OFF; @@ -141,7 +141,7 @@ static void lpc_init(device_t dev) outl(((on << 1) + 0x10), (pm10_bar + 0x10)); dword = inl(pm10_bar + 0x10); on = 8 - on; - printk_debug("Throttling CPU %2d.%1.1d percent.\n", + printk(BIOS_DEBUG, "Throttling CPU %2d.%1.1d percent.\n", (on * 12) + (on >> 1), (on & 1) * 5); } #if 0 @@ -250,7 +250,7 @@ static void ck804_lpc_enable_childrens_resources(device_t dev) continue; base = res->base; end = resource_end(res); - printk_debug("ck804 lpc decode:%s, base=0x%08lx, end=0x%08lx\r\n", dev_path(child), base, end); + printk(BIOS_DEBUG, "ck804 lpc decode:%s, base=0x%08lx, end=0x%08lx\r\n", dev_path(child), base, end); switch (base) { case 0x3f8: // COM1 reg |= (1 << 0); diff --git a/src/southbridge/nvidia/ck804/ck804_pci.c b/src/southbridge/nvidia/ck804/ck804_pci.c index 70ccdc6329..ccbbbd48a9 100644 --- a/src/southbridge/nvidia/ck804/ck804_pci.c +++ b/src/southbridge/nvidia/ck804/ck804_pci.c @@ -53,13 +53,13 @@ static void pci_init(struct device *dev) if (!pref || pref->base > mem->base) { dword = mem->base & (0xffff0000UL); - printk_debug("PCI DOMAIN mem base = 0x%010Lx\n", mem->base); + printk(BIOS_DEBUG, "PCI DOMAIN mem base = 0x%010Lx\n", mem->base); } else { dword = pref->base & (0xffff0000UL); - printk_debug("PCI DOMAIN pref base = 0x%010Lx\n", pref->base); + printk(BIOS_DEBUG, "PCI DOMAIN pref base = 0x%010Lx\n", pref->base); } - printk_debug("[0x50] <-- 0x%08x\n", dword); + printk(BIOS_DEBUG, "[0x50] <-- 0x%08x\n", dword); pci_write_config32(dev, 0x50, dword); /* TOM */ } diff --git a/src/southbridge/nvidia/ck804/ck804_sata.c b/src/southbridge/nvidia/ck804/ck804_sata.c index e9218abf3a..8eed906ce8 100644 --- a/src/southbridge/nvidia/ck804/ck804_sata.c +++ b/src/southbridge/nvidia/ck804/ck804_sata.c @@ -26,7 +26,7 @@ static void sata_com_reset(struct device *dev, unsigned reset) base = (uint32_t *) pci_read_config32(dev, 0x24); - printk_debug("base = %08lx\n", base); + printk(BIOS_DEBUG, "base = %08lx\n", base); if (reset) { *(base + 4) = 0xffffffff; @@ -51,7 +51,7 @@ static void sata_com_reset(struct device *dev, unsigned reset) return; dword = *(base + 0); - printk_debug("*(base+0)=%08x\r\n", dword); + printk(BIOS_DEBUG, "*(base+0)=%08x\r\n", dword); if (dword == 0x113) { loop = 200000; // 2 do { @@ -60,11 +60,11 @@ static void sata_com_reset(struct device *dev, unsigned reset) break; udelay(10); } while (--loop > 0); - printk_debug("loop=%d, *(base+4)=%08x\r\n", loop, dword); + printk(BIOS_DEBUG, "loop=%d, *(base+4)=%08x\r\n", loop, dword); } dword = *(base + 0x40); - printk_debug("*(base+0x40)=%08x\r\n", dword); + printk(BIOS_DEBUG, "*(base+0x40)=%08x\r\n", dword); if (dword == 0x113) { loop = 200000; //2 do { @@ -73,7 +73,7 @@ static void sata_com_reset(struct device *dev, unsigned reset) break; udelay(10); } while (--loop > 0); - printk_debug("loop=%d, *(base+0x44)=%08x\r\n", loop, dword); + printk(BIOS_DEBUG, "loop=%d, *(base+0x44)=%08x\r\n", loop, dword); } } #endif @@ -91,12 +91,12 @@ static void sata_init(struct device *dev) if (conf->sata1_enable) { /* Enable secondary SATA interface. */ dword |= (1 << 0); - printk_debug("SATA S \t"); + printk(BIOS_DEBUG, "SATA S \t"); } if (conf->sata0_enable) { /* Enable primary SATA interface. */ dword |= (1 << 1); - printk_debug("SATA P \n"); + printk(BIOS_DEBUG, "SATA P \n"); } #if 0 /* Write back */ diff --git a/src/southbridge/nvidia/mcp55/mcp55.c b/src/southbridge/nvidia/mcp55/mcp55.c index 4c07a60162..aa86cf3bc7 100644 --- a/src/southbridge/nvidia/mcp55/mcp55.c +++ b/src/southbridge/nvidia/mcp55/mcp55.c @@ -218,7 +218,7 @@ void mcp55_enable(device_t dev) // reg |= (1<<0); reg &= ~(0x3f<<4); if (reg != reg_old) { - printk_debug("mcp55.c pcie enabled\n"); + printk(BIOS_DEBUG, "mcp55.c pcie enabled\n"); pci_write_config32(sm_dev, 0xe4, reg); } #endif diff --git a/src/southbridge/nvidia/mcp55/mcp55_aza.c b/src/southbridge/nvidia/mcp55/mcp55_aza.c index b86530b7af..cea0b49e8c 100644 --- a/src/southbridge/nvidia/mcp55/mcp55_aza.c +++ b/src/southbridge/nvidia/mcp55/mcp55_aza.c @@ -80,7 +80,7 @@ static int codec_detect(uint8_t *base) /* 6 */ if(!dword) { set_bits(base + 0x08, 1, 0); - printk_debug("No codec!\n"); + printk(BIOS_DEBUG, "No codec!\n"); return 0; } return dword; @@ -186,15 +186,15 @@ static void codec_init(uint8_t *base, int addr) dword = read32(base + 0x64); /* 2 */ - printk_debug("codec viddid: %08x\n", dword); + printk(BIOS_DEBUG, "codec viddid: %08x\n", dword); verb_size = find_verb(dword, &verb); if(!verb_size) { - printk_debug("No verb!\n"); + printk(BIOS_DEBUG, "No verb!\n"); return; } - printk_debug("verb_size: %d\n", verb_size); + printk(BIOS_DEBUG, "verb_size: %d\n", verb_size); /* 3 */ for(i=0; i<verb_size; i++) { do { @@ -207,7 +207,7 @@ static void codec_init(uint8_t *base, int addr) dword = read32(base + 0x68); } while ((dword & 3) != 2); } - printk_debug("verb loaded!\n"); + printk(BIOS_DEBUG, "verb loaded!\n"); } static void codecs_init(uint8_t *base, uint32_t codec_mask) @@ -230,12 +230,12 @@ static void aza_init(struct device *dev) return; base =(uint8_t *) res->base; - printk_debug("base = %08x\n", base); + printk(BIOS_DEBUG, "base = %08x\n", base); codec_mask = codec_detect(base); if(codec_mask) { - printk_debug("codec_mask = %02x\n", codec_mask); + printk(BIOS_DEBUG, "codec_mask = %02x\n", codec_mask); codecs_init(base, codec_mask); } } diff --git a/src/southbridge/nvidia/mcp55/mcp55_fadt.c b/src/southbridge/nvidia/mcp55/mcp55_fadt.c index 212cbe6f3a..7c7ad6954c 100644 --- a/src/southbridge/nvidia/mcp55/mcp55_fadt.c +++ b/src/southbridge/nvidia/mcp55/mcp55_fadt.c @@ -49,7 +49,7 @@ void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) memcpy(header->asl_compiler_id, "CORE", 4); header->asl_compiler_revision = 42; - printk_info("ACPI: pm_base: %u...\n", pm_base); + printk(BIOS_INFO, "ACPI: pm_base: %u...\n", pm_base); fadt->firmware_ctrl = facs; fadt->dsdt = dsdt; diff --git a/src/southbridge/nvidia/mcp55/mcp55_ide.c b/src/southbridge/nvidia/mcp55/mcp55_ide.c index e62a5477d9..fac5997513 100644 --- a/src/southbridge/nvidia/mcp55/mcp55_ide.c +++ b/src/southbridge/nvidia/mcp55/mcp55_ide.c @@ -43,12 +43,12 @@ static void ide_init(struct device *dev) if (conf->ide1_enable) { /* Enable secondary ide interface */ word |= (1<<0); - printk_debug("IDE1 \t"); + printk(BIOS_DEBUG, "IDE1 \t"); } if (conf->ide0_enable) { /* Enable primary ide interface */ word |= (1<<1); - printk_debug("IDE0\n"); + printk(BIOS_DEBUG, "IDE0\n"); } word |= (1<<12); diff --git a/src/southbridge/nvidia/mcp55/mcp55_lpc.c b/src/southbridge/nvidia/mcp55/mcp55_lpc.c index c247d98be1..869e8392e2 100644 --- a/src/southbridge/nvidia/mcp55/mcp55_lpc.c +++ b/src/southbridge/nvidia/mcp55/mcp55_lpc.c @@ -80,7 +80,7 @@ static void enable_hpet(struct device *dev) pci_write_config32(dev,0x44, 0xfed00001); hpet_address=pci_read_config32(dev,0x44)& 0xfffffffe; - printk_debug("enabling HPET @0x%x\n", hpet_address); + printk(BIOS_DEBUG, "enabling HPET @0x%x\n", hpet_address); } static void lpc_init(device_t dev) @@ -108,7 +108,7 @@ static void lpc_init(device_t dev) byte |= 0x40; } pci_write_config8(dev, PREVIOUS_POWER_STATE, byte); - printk_info("set power %s after power fail\n", on?"on":"off"); + printk(BIOS_INFO, "set power %s after power fail\n", on?"on":"off"); #endif /* Throttle the CPU speed down for testing */ on = SLOW_CPU_OFF; @@ -120,7 +120,7 @@ static void lpc_init(device_t dev) outl(((on<<1)+0x10) ,(pm10_bar + 0x10)); dword = inl(pm10_bar + 0x10); on = 8-on; - printk_debug("Throttling CPU %2d.%1.1d percent.\n", + printk(BIOS_DEBUG, "Throttling CPU %2d.%1.1d percent.\n", (on*12)+(on>>1),(on&1)*5); } @@ -224,7 +224,7 @@ static void mcp55_lpc_enable_childrens_resources(device_t dev) if(!(res->flags & IORESOURCE_IO)) continue; base = res->base; end = resource_end(res); - printk_debug("mcp55 lpc decode:%s, base=0x%08x, end=0x%08x\n",dev_path(child),base, end); + printk(BIOS_DEBUG, "mcp55 lpc decode:%s, base=0x%08x, end=0x%08x\n",dev_path(child),base, end); switch(base) { case 0x3f8: // COM1 reg |= (1<<0); break; diff --git a/src/southbridge/nvidia/mcp55/mcp55_nic.c b/src/southbridge/nvidia/mcp55/mcp55_nic.c index d3b92b97bb..92ea633a20 100644 --- a/src/southbridge/nvidia/mcp55/mcp55_nic.c +++ b/src/southbridge/nvidia/mcp55/mcp55_nic.c @@ -83,13 +83,13 @@ static void phy_detect(uint8_t *base) val = phy_read(base, phyaddr, 2); if (val < 0 || val == 0xffff) continue; id |= ((val & 0xffff)<<16); - printk_debug("MCP55 MAC PHY ID 0x%08x PHY ADDR %d\n", id, i); + printk(BIOS_DEBUG, "MCP55 MAC PHY ID 0x%08x PHY ADDR %d\n", id, i); // if((id == 0xe0180000) || (id==0x0032cc00)) break; } if(i>32) { - printk_debug("MCP55 MAC PHY not found\n"); + printk(BIOS_DEBUG, "MCP55 MAC PHY not found\n"); } } diff --git a/src/southbridge/nvidia/mcp55/mcp55_pci.c b/src/southbridge/nvidia/mcp55/mcp55_pci.c index 3bc3a1ab18..02b0124884 100644 --- a/src/southbridge/nvidia/mcp55/mcp55_pci.c +++ b/src/southbridge/nvidia/mcp55/mcp55_pci.c @@ -75,13 +75,13 @@ static void pci_init(struct device *dev) if (!pref || pref->base > mem->base) { dword = mem->base & (0xffff0000UL); - printk_debug("PCI DOMAIN mem base = 0x%010Lx\n", mem->base); + printk(BIOS_DEBUG, "PCI DOMAIN mem base = 0x%010Lx\n", mem->base); } else { dword = pref->base & (0xffff0000UL); - printk_debug("PCI DOMAIN pref base = 0x%010Lx\n", pref->base); + printk(BIOS_DEBUG, "PCI DOMAIN pref base = 0x%010Lx\n", pref->base); } - printk_debug("[0x50] <-- 0x%08x\n", dword); + printk(BIOS_DEBUG, "[0x50] <-- 0x%08x\n", dword); pci_write_config32(dev, 0x50, dword); /* TOM */ } diff --git a/src/southbridge/nvidia/mcp55/mcp55_sata.c b/src/southbridge/nvidia/mcp55/mcp55_sata.c index 1b40aa0983..8df5f6bcbd 100644 --- a/src/southbridge/nvidia/mcp55/mcp55_sata.c +++ b/src/southbridge/nvidia/mcp55/mcp55_sata.c @@ -43,16 +43,16 @@ static void sata_init(struct device *dev) if (conf->sata1_enable) { /* Enable secondary SATA interface */ dword |= (1<<0); - printk_debug("SATA S \t"); + printk(BIOS_DEBUG, "SATA S \t"); } if (conf->sata0_enable) { /* Enable primary SATA interface */ dword |= (1<<1); - printk_debug("SATA P \n"); + printk(BIOS_DEBUG, "SATA P \n"); } } else { dword |= (1<<1) | (1<<0); - printk_debug("SATA P and S \n"); + printk(BIOS_DEBUG, "SATA P and S \n"); } diff --git a/src/southbridge/ricoh/rl5c476/rl5c476.c b/src/southbridge/ricoh/rl5c476/rl5c476.c index 72d0390cd5..5d669e78ae 100644 --- a/src/southbridge/ricoh/rl5c476/rl5c476.c +++ b/src/southbridge/ricoh/rl5c476/rl5c476.c @@ -38,9 +38,9 @@ static void rl5c476_init(device_t dev) unsigned char *base; /* cardbus controller function 1 for CF Socket */ - printk_debug("Ricoh RL5c476: Initializing.\n"); + printk(BIOS_DEBUG, "Ricoh RL5c476: Initializing.\n"); - printk_debug("CF Base = %0x\n",cf_base); + printk(BIOS_DEBUG, "CF Base = %0x\n",cf_base); /* misc control register */ pci_write_config16(dev,0x82,0x00a0); @@ -48,7 +48,7 @@ static void rl5c476_init(device_t dev) /* set up second slot as compact flash port if asked to do so */ if (!enable_cf_boot) { - printk_debug("CF boot not enabled.\n"); + printk(BIOS_DEBUG, "CF boot not enabled.\n"); return; } @@ -152,7 +152,7 @@ static void rl5c476_init(device_t dev) */ unsigned char *cptr; cptr = (unsigned char *)(cf_base + 0x200); - printk_debug("CF Config = %x\n",*cptr); + printk(BIOS_DEBUG, "CF Config = %x\n",*cptr); /* Set CF to decode 16 IO bytes on any 16 byte boundary - * rely on the io windows of the bridge set up above to @@ -184,12 +184,12 @@ void rl5c476_read_resources(device_t dev) void rl5c476_set_resources(device_t dev) { struct resource *resource; - printk_debug("%s In set resources \n",dev_path(dev)); + printk(BIOS_DEBUG, "%s In set resources \n",dev_path(dev)); if( enable_cf_boot && (PCI_FUNC(dev->path.pci.devfn) == 1)){ resource = find_resource(dev,1); if( !(resource->flags & IORESOURCE_STORED) ){ resource->flags |= IORESOURCE_STORED ; - printk_debug("%s 1 ==> %x\n", dev_path(dev), resource->base); + printk(BIOS_DEBUG, "%s 1 ==> %x\n", dev_path(dev), resource->base); cf_base = resource->base; } } diff --git a/src/southbridge/sis/sis966/sis761.c b/src/southbridge/sis/sis966/sis761.c index b4eb48d559..43a235b01f 100644 --- a/src/southbridge/sis/sis966/sis761.c +++ b/src/southbridge/sis/sis966/sis761.c @@ -72,27 +72,27 @@ static inline msr_t rdmsr(unsigned index) static void sis761_read_resources(device_t dev) { /* Read the generic PCI resources */ - printk_debug("sis761_read_resources ------->\n"); + printk(BIOS_DEBUG, "sis761_read_resources ------->\n"); pci_dev_read_resources(dev); /* If we are not the first processor don't allocate the gart apeture */ if (dev->path.pci.devfn != PCI_DEVFN(0x0, 0)) { - printk_debug("sis761_not_the_first_processor !!!\n"); + printk(BIOS_DEBUG, "sis761_not_the_first_processor !!!\n"); return; } - printk_debug("sis761_read_resources <-------\n"); + printk(BIOS_DEBUG, "sis761_read_resources <-------\n"); return; } static void sis761_set_resources(device_t dev) { - printk_debug("sis761_set_resources ------->\n"); + printk(BIOS_DEBUG, "sis761_set_resources ------->\n"); /* Set the generic PCI resources */ pci_dev_set_resources(dev); - printk_debug("sis761_set_resources <-------\n"); + printk(BIOS_DEBUG, "sis761_set_resources <-------\n"); } static void sis761_init(struct device *dev) @@ -102,14 +102,14 @@ static void sis761_init(struct device *dev) needs_reset = 0; - printk_debug("sis761_init: ---------->\n"); + printk(BIOS_DEBUG, "sis761_init: ---------->\n"); msr = rdmsr(0xC001001A); pci_write_config16(dev, 0x8E, msr.lo >> 16); // Topbound pci_write_config8(dev, 0x7F, 0x08); // ACPI Base outb(inb(0x856) | 0x40, 0x856); // Auto-Reset Function - printk_debug("sis761_init: <----------\n"); + printk(BIOS_DEBUG, "sis761_init: <----------\n"); } diff --git a/src/southbridge/sis/sis966/sis966_aza.c b/src/southbridge/sis/sis966/sis966_aza.c index 1dc91ae45d..013f5895c1 100644 --- a/src/southbridge/sis/sis966/sis966_aza.c +++ b/src/southbridge/sis/sis966/sis966_aza.c @@ -101,23 +101,23 @@ static int codec_detect(uint8_t *base) int idx=0; /* 1 */ // controller reset - printk_debug("controller reset\n"); + printk(BIOS_DEBUG, "controller reset\n"); set_bits(base + 0x08, 1, 1); do{ dword = read32(base + 0x08)&0x1; - if(idx++>1000) { printk_debug("controller reset fail !!! \n"); break;} + if(idx++>1000) { printk(BIOS_DEBUG, "controller reset fail !!! \n"); break;} } while (dword !=1); dword=send_verb(base,0x000F0000); // get codec VendorId and DeviceId if(dword==0) { - printk_debug("No codec!\n"); + printk(BIOS_DEBUG, "No codec!\n"); return 0; } - printk_debug("Codec ID = %lx\n", dword); + printk(BIOS_DEBUG, "Codec ID = %lx\n", dword); dword=0x1; return dword; @@ -219,20 +219,20 @@ static void codec_init(uint8_t *base, int addr) dword = read32(base + 0x64); /* 2 */ - printk_debug("codec viddid: %08x\n", dword); + printk(BIOS_DEBUG, "codec viddid: %08x\n", dword); verb_size = find_verb(dword, &verb); if(!verb_size) { - printk_debug("No verb!\n"); + printk(BIOS_DEBUG, "No verb!\n"); return; } - printk_debug("verb_size: %d\n", verb_size); + printk(BIOS_DEBUG, "verb_size: %d\n", verb_size); /* 3 */ for(i=0; i<verb_size; i++) { send_verb(base,verb[i]); } - printk_debug("verb loaded!\n"); + printk(BIOS_DEBUG, "verb loaded!\n"); } static void codecs_init(uint8_t *base, uint32_t codec_mask) @@ -293,12 +293,12 @@ static void aza_init(struct device *dev) return; base =(uint8_t *) res->base; - printk_debug("base = %08x\n", base); + printk(BIOS_DEBUG, "base = %08x\n", base); codec_mask = codec_detect(base); if(codec_mask) { - printk_debug("codec_mask = %02x\n", codec_mask); + printk(BIOS_DEBUG, "codec_mask = %02x\n", codec_mask); codecs_init(base, codec_mask); } diff --git a/src/southbridge/sis/sis966/sis966_early_smbus.c b/src/southbridge/sis/sis966/sis966_early_smbus.c index cb6358bf8b..98b824f88a 100644 --- a/src/southbridge/sis/sis966/sis966_early_smbus.c +++ b/src/southbridge/sis/sis966/sis966_early_smbus.c @@ -481,23 +481,23 @@ void sis_init_stage2(void) // ========================== NB ============================= - printk_debug("Init NorthBridge sis761 -------->\n"); + printk(BIOS_DEBUG, "Init NorthBridge sis761 -------->\n"); dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS761), 0); msr = rdmsr(0xC001001A); - printk_debug("Memory Top Bound %lx\n",msr.lo ); + printk(BIOS_DEBUG, "Memory Top Bound %lx\n",msr.lo ); temp16=(pci_read_config8(dev, 0x4C) & 0xE0) >> 5; temp16=0x0001<<(temp16-1); temp16<<=8; - printk_debug("Integrated VGA Shared memory size=%dM bytes\n", temp16 >> 4); + printk(BIOS_DEBUG, "Integrated VGA Shared memory size=%dM bytes\n", temp16 >> 4); pci_write_config16(dev, 0x8E, (msr.lo >> 16) -temp16*1); pci_write_config8(dev, 0x7F, 0x08); // ACPI Base outb(inb(0x856) | 0x40, 0x856); // Auto-Reset Function // ========================== ACPI ============================= i=0; - printk_debug("Init ACPI -------->\n"); + printk(BIOS_DEBUG, "Init ACPI -------->\n"); do { temp8 = inb(0x800 + SiS_ACPI_2_init[i][0]); temp8 &= SiS_ACPI_2_init[i][1]; @@ -507,7 +507,7 @@ void sis_init_stage2(void) }while(SiS_ACPI_2_init[i][0] != 0); // ========================== Misc ============================= - printk_debug("Init Misc -------->\n"); + printk(BIOS_DEBUG, "Init Misc -------->\n"); dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS966_LPC), 0); /* R77h Internal PCI Device Enable 1 (Power On Value = 0h) @@ -533,7 +533,7 @@ void sis_init_stage2(void) pci_write_config8(dev, 0x7E, 0x00); // azalia controller enable temp8=inb(0x878)|0x4; //bit2=1 enable Azalia =0 enable AC97 outb(temp8, 0x878); // ACPI select AC97 or HDA controller - printk_debug("Audio select %x\n",inb(0x878)); + printk(BIOS_DEBUG, "Audio select %x\n",inb(0x878)); dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS966_SATA), 0); @@ -550,7 +550,7 @@ static void enable_smbus(void) { device_t dev; uint8_t temp8; - printk_debug("enable_smbus -------->\n"); + printk(BIOS_DEBUG, "enable_smbus -------->\n"); dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS966_LPC), 0); @@ -561,7 +561,7 @@ static void enable_smbus(void) temp8=pci_read_config8(dev, 0x76); // Enable SMBUS pci_write_config8(dev, 0x76, temp8 | 0x03); - printk_debug("enable_smbus <--------\n"); + printk(BIOS_DEBUG, "enable_smbus <--------\n"); } static int smbus_read_byte(unsigned device, unsigned address) diff --git a/src/southbridge/sis/sis966/sis966_ide.c b/src/southbridge/sis/sis966/sis966_ide.c index 62841e5098..1ee583f889 100644 --- a/src/southbridge/sis/sis966/sis966_ide.c +++ b/src/southbridge/sis/sis966/sis966_ide.c @@ -123,12 +123,12 @@ print_debug("IDE_INIT:---------->\n"); if (conf->ide1_enable) { /* Enable secondary ide interface */ word |= (1<<0); - printk_debug("IDE1 \t"); + printk(BIOS_DEBUG, "IDE1 \t"); } if (conf->ide0_enable) { /* Enable primary ide interface */ word |= (1<<1); - printk_debug("IDE0\n"); + printk(BIOS_DEBUG, "IDE0\n"); } word |= (1<<12); diff --git a/src/southbridge/sis/sis966/sis966_lpc.c b/src/southbridge/sis/sis966/sis966_lpc.c index 0786fcda79..c23e628970 100644 --- a/src/southbridge/sis/sis966/sis966_lpc.c +++ b/src/southbridge/sis/sis966/sis966_lpc.c @@ -92,7 +92,7 @@ static void lpc_init(device_t dev) int on; int nmi_option; - printk_debug("LPC_INIT -------->\n"); + printk(BIOS_DEBUG, "LPC_INIT -------->\n"); pc_keyboard_init(0); lpc_usb_legacy_init(dev); @@ -109,7 +109,7 @@ static void lpc_init(device_t dev) byte |= 0x40; } pci_write_config8(dev, PREVIOUS_POWER_STATE, byte); - printk_info("set power %s after power fail\n", on?"on":"off"); + printk(BIOS_INFO, "set power %s after power fail\n", on?"on":"off"); /* Throttle the CPU speed down for testing */ on = SLOW_CPU_OFF; @@ -121,7 +121,7 @@ static void lpc_init(device_t dev) outl(((on<<1)+0x10) ,(pm10_bar + 0x10)); dword = inl(pm10_bar + 0x10); on = 8-on; - printk_debug("Throttling CPU %2d.%1.1d percent.\n", + printk(BIOS_DEBUG, "Throttling CPU %2d.%1.1d percent.\n", (on*12)+(on>>1),(on&1)*5); } @@ -151,7 +151,7 @@ static void lpc_init(device_t dev) /* Initialize isa dma */ isa_dma_init(); - printk_debug("LPC_INIT <--------\n"); + printk(BIOS_DEBUG, "LPC_INIT <--------\n"); } static void sis966_lpc_read_resources(device_t dev) @@ -214,7 +214,7 @@ static void sis966_lpc_enable_childrens_resources(device_t dev) if(!(res->flags & IORESOURCE_IO)) continue; base = res->base; end = resource_end(res); - printk_debug("sis966 lpc decode:%s, base=0x%08x, end=0x%08x\n",dev_path(child),base, end); + printk(BIOS_DEBUG, "sis966 lpc decode:%s, base=0x%08x, end=0x%08x\n",dev_path(child),base, end); switch(base) { case 0x3f8: // COM1 reg |= (1<<0); break; diff --git a/src/southbridge/sis/sis966/sis966_nic.c b/src/southbridge/sis/sis966/sis966_nic.c index 9fadcf9419..62017360e7 100644 --- a/src/southbridge/sis/sis966/sis966_nic.c +++ b/src/southbridge/sis/sis966/sis966_nic.c @@ -75,12 +75,12 @@ static void readApcMacAddr(void) outl(0x80001048,0xcf8); outl((inl(0xcfc) & 0xfffffffd),0xcfc ); // enable IO78/79h for APC Index/Data - printk_debug("MAC addr in APC = "); + printk(BIOS_DEBUG, "MAC addr in APC = "); for(i = 0x9 ; i <=0xe ; i++) { - printk_debug("%2.2x",readApcByte(i)); + printk(BIOS_DEBUG, "%2.2x",readApcByte(i)); } - printk_debug("\n"); + printk(BIOS_DEBUG, "\n"); /* Set APC Reload */ writeApcByte(0x7,readApcByte(0x7)&0xf7); @@ -192,7 +192,7 @@ static int phy_read(uint32_t base, unsigned phy_addr, unsigned phy_reg) mdelay(20); ulValue = read32(base+0x44); } while((ulValue & SMI_REQUEST) != 0); - //printk_debug("base %x cmd %lx ret val %lx\n", tmp,Read_Cmd,ulValue); + //printk(BIOS_DEBUG, "base %x cmd %lx ret val %lx\n", tmp,Read_Cmd,ulValue); usData=(ulValue>>16); @@ -227,7 +227,7 @@ static int phy_detect(uint32_t base,uint16_t *PhyAddr) //BOOL PHY_Detect() if(!bFoundPhy) { - printk_debug("PHY not found !!!! \n"); + printk(BIOS_DEBUG, "PHY not found !!!! \n"); } *PhyAddr=PhyAddress; @@ -270,15 +270,15 @@ static void nic_init(struct device *dev) if(!res) { - printk_debug("NIC Cannot find resource..\r\n"); + printk(BIOS_DEBUG, "NIC Cannot find resource..\r\n"); return; } base = res->base; - printk_debug("NIC base address %lx\n",base); + printk(BIOS_DEBUG, "NIC base address %lx\n",base); if(!(val=phy_detect(base,&PhyAddr))) { - printk_debug("PHY detect fail !!!!\r\n"); + printk(BIOS_DEBUG, "PHY detect fail !!!!\r\n"); return; } @@ -291,7 +291,7 @@ static void nic_init(struct device *dev) // if that is valid we will use that - printk_debug("EEPROM contents %x \n",ReadEEprom( dev, base, 0LL)); + printk(BIOS_DEBUG, "EEPROM contents %x \n",ReadEEprom( dev, base, 0LL)); for(i=0;i<3;i++) { //status = smbus_read_byte(dev_eeprom, i); ulValue=ReadEEprom( dev, base, i+3L); @@ -302,7 +302,7 @@ static void nic_init(struct device *dev) } }else{ // read MAC address from firmware - printk_debug("EEPROM invalid!!\nReg 0x38h=%.8lx \n",ulValue); + printk(BIOS_DEBUG, "EEPROM invalid!!\nReg 0x38h=%.8lx \n",ulValue); MacAddr[0]=read16(0xffffffc0); // mac address store at here MacAddr[1]=read16(0xffffffc2); MacAddr[2]=read16(0xffffffc4); diff --git a/src/southbridge/sis/sis966/sis966_sata.c b/src/southbridge/sis/sis966/sis966_sata.c index b15869c677..7fcee82f29 100644 --- a/src/southbridge/sis/sis966/sis966_sata.c +++ b/src/southbridge/sis/sis966/sis966_sata.c @@ -141,7 +141,7 @@ for (i=0;i<10;i++){ temp32=0; temp32= pci_read_config32(dev, 0xC0); for ( j=0;j<0xFFFF;j++); - printk_debug("status= %x\n",temp32); + printk(BIOS_DEBUG, "status= %x\n",temp32); if (((temp32&0xF) == 0x3) || ((temp32&0xF) == 0x0)) break; } diff --git a/src/southbridge/sis/sis966/sis966_usb2.c b/src/southbridge/sis/sis966/sis966_usb2.c index 35dec13453..437583d12f 100644 --- a/src/southbridge/sis/sis966/sis966_usb2.c +++ b/src/southbridge/sis/sis966/sis966_usb2.c @@ -95,7 +95,7 @@ static void usb2_init(struct device *dev) return; base =(uint8_t *) res->base; - printk_debug("base = %08x\n", base); + printk(BIOS_DEBUG, "base = %08x\n", base); write32(base+0x20, 0x2); //----------------------------------------------------------- diff --git a/src/southbridge/ti/pci7420/pci7420_cardbus.c b/src/southbridge/ti/pci7420/pci7420_cardbus.c index 78fb3ba1f8..7165822ea7 100644 --- a/src/southbridge/ti/pci7420/pci7420_cardbus.c +++ b/src/southbridge/ti/pci7420/pci7420_cardbus.c @@ -41,10 +41,10 @@ static void pci7420_cardbus_init(device_t dev) struct southbridge_ti_pci7420_config *config = dev->chip_info; int smartcard_enabled = 0; - printk_debug("TI PCI7420/7620 init\n"); + printk(BIOS_DEBUG, "TI PCI7420/7620 init\n"); if (!config) { - printk_debug("PCI7420: No configuration found.\n"); + printk(BIOS_DEBUG, "PCI7420: No configuration found.\n"); } else { smartcard_enabled = config->smartcard_enabled; } @@ -90,11 +90,11 @@ void pci7420_cardbus_read_resources(device_t dev) void pci7420_cardbus_set_resources(device_t dev) { - printk_debug("%s In set resources \n",dev_path(dev)); + printk(BIOS_DEBUG, "%s In set resources \n",dev_path(dev)); pci_dev_set_resources(dev); - printk_debug("%s done set resources \n",dev_path(dev)); + printk(BIOS_DEBUG, "%s done set resources \n",dev_path(dev)); } static struct device_operations ti_pci7420_ops = { diff --git a/src/southbridge/ti/pci7420/pci7420_firewire.c b/src/southbridge/ti/pci7420/pci7420_firewire.c index 01ca4878f7..4d855b30b5 100644 --- a/src/southbridge/ti/pci7420/pci7420_firewire.c +++ b/src/southbridge/ti/pci7420/pci7420_firewire.c @@ -32,7 +32,7 @@ static void pci7420_firewire_init(device_t dev) { u8 reg8; - printk_debug("TI PCI7420/7620 FireWire init\n"); + printk(BIOS_DEBUG, "TI PCI7420/7620 FireWire init\n"); #ifdef ODD_IRQ_FIXUP /* This is a workaround for buggy kernels. This should diff --git a/src/southbridge/via/k8t890/k8m890_chrome.c b/src/southbridge/via/k8t890/k8m890_chrome.c index fdf55aa929..2cbd9382ae 100644 --- a/src/southbridge/via/k8t890/k8m890_chrome.c +++ b/src/southbridge/via/k8t890/k8m890_chrome.c @@ -125,7 +125,7 @@ chrome_init(struct device *dev) fb_size = k8m890_host_fb_size_get(); if (!fb_size) { - printk_warning("Chrome: Device has not been initialised in the" + printk(BIOS_WARNING, "Chrome: Device has not been initialised in the" " ramcontroller!\n"); return; } @@ -133,11 +133,11 @@ chrome_init(struct device *dev) fb_address = pci_read_config32(dev, 0x10); fb_address &= ~0x0F; if (!fb_address) { - printk_warning("Chrome: No FB BAR assigned!\n"); + printk(BIOS_WARNING, "Chrome: No FB BAR assigned!\n"); return; } - printk_info("Chrome: Using %dMB Framebuffer at 0x%08X.\n", + printk(BIOS_INFO, "Chrome: Using %dMB Framebuffer at 0x%08X.\n", fb_size, fb_address); //k8m890_host_fb_direct_set(fb_address); @@ -154,7 +154,7 @@ chrome_init(struct device *dev) vga_console_init(); #endif - printk_info("Chrome VGA Textmode initialized.\n"); + printk(BIOS_INFO, "Chrome VGA Textmode initialized.\n"); #if CONFIG_CONSOLE_VGA == 0 /* if we don't have console, at least print something... */ diff --git a/src/southbridge/via/k8t890/k8t890_dram.c b/src/southbridge/via/k8t890/k8t890_dram.c index 84a41a46b8..ac67d4a5b6 100644 --- a/src/southbridge/via/k8t890/k8t890_dram.c +++ b/src/southbridge/via/k8t890/k8t890_dram.c @@ -82,7 +82,7 @@ static void get_memres(void *gp, struct device *dev, struct resource *res) unsigned int *fbsize = (unsigned int *) gp; uint64_t proposed_base = res->base + res->size - *fbsize; - printk_debug("get_memres: res->base=%llx res->size=%llx %d %d %d\n", + printk(BIOS_DEBUG, "get_memres: res->base=%llx res->size=%llx %d %d %d\n", res->base, res->size, (res->size > *fbsize), (!(proposed_base & (*fbsize - 1))), (proposed_base < ((uint64_t) 0xffffffff))); @@ -99,7 +99,7 @@ extern uint64_t high_tables_base, high_tables_size; if ((high_tables_base) && ((high_tables_base > proposed_base) && (high_tables_base < (res->base + res->size)))) { high_tables_base = proposed_base - high_tables_size; - printk_debug("Moving the high_tables_base pointer to " + printk(BIOS_DEBUG, "Moving the high_tables_base pointer to " "new base %llx\n", high_tables_base); } #endif @@ -140,12 +140,12 @@ static void dram_init_fb(struct device *dev) ret = get_option(&fbbits, "videoram_size"); if (ret) { - printk_warning("Failed to get videoram size (error %d), using default.\n", ret); + printk(BIOS_WARNING, "Failed to get videoram size (error %d), using default.\n", ret); fbbits = 5; } if ((fbbits < 1) || (fbbits > 7)) { - printk_warning("Invalid videoram size (%d), using default.\n", + printk(BIOS_WARNING, "Invalid videoram size (%d), using default.\n", 4 << fbbits); fbbits = 5; } @@ -159,14 +159,14 @@ static void dram_init_fb(struct device *dev) /* no space for FB */ if (!resmax) { - printk_err("VIA FB: no space for framebuffer in RAM\n"); + printk(BIOS_ERR, "VIA FB: no space for framebuffer in RAM\n"); return; } proposed_base = resmax->base + resmax->size - fbsize; resmax->size -= fbsize; - printk_info("K8M890: Using a %dMB framebuffer.\n", 4 << fbbits); + printk(BIOS_INFO, "K8M890: Using a %dMB framebuffer.\n", 4 << fbbits); /* Step 1: enable UMA but no FB */ pci_write_config8(dev, 0xa1, 0x80); diff --git a/src/southbridge/via/k8t890/k8t890_early_car.c b/src/southbridge/via/k8t890/k8t890_early_car.c index 2b0c9e1609..a0a269bb94 100644 --- a/src/southbridge/via/k8t890/k8t890_early_car.c +++ b/src/southbridge/via/k8t890/k8t890_early_car.c @@ -114,7 +114,7 @@ u8 k8t890_early_setup_ht(void) int s3_save_nvram_early(u32 dword, int size, int nvram_pos) { - printk_debug("Writing %x of size %d to nvram pos: %d\n", dword, size, nvram_pos); + printk(BIOS_DEBUG, "Writing %x of size %d to nvram pos: %d\n", dword, size, nvram_pos); switch (size) { case 1: outb((dword & 0xff), K8T890_NVRAM_IO_BASE+nvram_pos); @@ -149,6 +149,6 @@ int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos) { nvram_pos +=4; break; } - printk_debug("Loading %x of size %d to nvram pos:%d\n", * old_dword, size, nvram_pos-size); + printk(BIOS_DEBUG, "Loading %x of size %d to nvram pos:%d\n", * old_dword, size, nvram_pos-size); return nvram_pos; } diff --git a/src/southbridge/via/k8t890/k8t890_pcie.c b/src/southbridge/via/k8t890/k8t890_pcie.c index 645296d40f..804398cf88 100644 --- a/src/southbridge/via/k8t890/k8t890_pcie.c +++ b/src/southbridge/via/k8t890/k8t890_pcie.c @@ -28,7 +28,7 @@ static void peg_init(struct device *dev) { u8 reg; - printk_debug("Configuring PCIe PEG\n"); + printk(BIOS_DEBUG, "Configuring PCIe PEG\n"); dump_south(dev); /* Disable link. */ @@ -68,7 +68,7 @@ static void pcie_init(struct device *dev) { u8 reg; - printk_debug("Configuring PCIe PEXs\n"); + printk(BIOS_DEBUG, "Configuring PCIe PEXs\n"); dump_south(dev); /* Disable link. */ diff --git a/src/southbridge/via/vt8231/vt8231.c b/src/southbridge/via/vt8231/vt8231.c index 5f8ab45009..f943524665 100644 --- a/src/southbridge/via/vt8231/vt8231.c +++ b/src/southbridge/via/vt8231/vt8231.c @@ -14,7 +14,7 @@ static device_t lpc_dev; void hard_reset(void) { - printk_err("NO HARD RESET ON VT8231! FIX ME!\n"); + printk(BIOS_ERR, "NO HARD RESET ON VT8231! FIX ME!\n"); } static void keyboard_on(void) diff --git a/src/southbridge/via/vt8231/vt8231_acpi.c b/src/southbridge/via/vt8231/vt8231_acpi.c index 87c5e876fd..6cbf4c591f 100644 --- a/src/southbridge/via/vt8231/vt8231_acpi.c +++ b/src/southbridge/via/vt8231/vt8231_acpi.c @@ -6,7 +6,7 @@ static void acpi_init(struct device *dev) { - printk_debug("Configuring VIA ACPI\n"); + printk(BIOS_DEBUG, "Configuring VIA ACPI\n"); // Set ACPI base address to IO 0x4000 pci_write_config32(dev, 0x48, 0x4001); diff --git a/src/southbridge/via/vt8231/vt8231_ide.c b/src/southbridge/via/vt8231/vt8231_ide.c index a151ca06c9..c1df5ef5cd 100644 --- a/src/southbridge/via/vt8231/vt8231_ide.c +++ b/src/southbridge/via/vt8231/vt8231_ide.c @@ -19,22 +19,22 @@ static void ide_init(struct device *dev) */ /* - printk_info("%s: enabling compatibility IDE addresses\n", __func__); + printk(BIOS_INFO, "%s: enabling compatibility IDE addresses\n", __func__); enables = pci_read_config8(dev, 0x42); - printk_debug("enables in reg 0x42 0x%x\n", enables); + printk(BIOS_DEBUG, "enables in reg 0x42 0x%x\n", enables); enables &= ~0xc0; // compatability mode pci_write_config8(dev, 0x42, enables); enables = pci_read_config8(dev, 0x42); - printk_debug("enables in reg 0x42 read back as 0x%x\n", enables); + printk(BIOS_DEBUG, "enables in reg 0x42 read back as 0x%x\n", enables); */ } enables = pci_read_config8(dev, 0x40); - printk_debug("enables in reg 0x40 0x%x\n", enables); + printk(BIOS_DEBUG, "enables in reg 0x40 0x%x\n", enables); enables |= 3; pci_write_config8(dev, 0x40, enables); enables = pci_read_config8(dev, 0x40); - printk_debug("enables in reg 0x40 read back as 0x%x\n", enables); + printk(BIOS_DEBUG, "enables in reg 0x40 read back as 0x%x\n", enables); // Enable prefetch buffers enables = pci_read_config8(dev, 0x41); @@ -58,7 +58,7 @@ static void ide_init(struct device *dev) // kevinh@ispiri.com - the standard linux drivers seem ass slow when // used in native mode - I've changed back to classic enables = pci_read_config8(dev, 0x9); - printk_debug("enables in reg 0x9 0x%x\n", enables); + printk(BIOS_DEBUG, "enables in reg 0x9 0x%x\n", enables); // by the book, set the low-order nibble to 0xa. if (conf->enable_native_ide) { enables &= ~0xf; @@ -70,11 +70,11 @@ static void ide_init(struct device *dev) pci_write_config8(dev, 0x9, enables); enables = pci_read_config8(dev, 0x9); - printk_debug("enables in reg 0x9 read back as 0x%x\n", enables); + printk(BIOS_DEBUG, "enables in reg 0x9 read back as 0x%x\n", enables); // standard bios sets master bit. enables = pci_read_config8(dev, 0x4); - printk_debug("command in reg 0x4 0x%x\n", enables); + printk(BIOS_DEBUG, "command in reg 0x4 0x%x\n", enables); enables |= 7; // No need for stepping - kevinh@ispiri.com @@ -82,7 +82,7 @@ static void ide_init(struct device *dev) pci_write_config8(dev, 0x4, enables); enables = pci_read_config8(dev, 0x4); - printk_debug("command in reg 0x4 reads back as 0x%x\n", enables); + printk(BIOS_DEBUG, "command in reg 0x4 reads back as 0x%x\n", enables); if (!conf->enable_native_ide) { // Use compatability mode - per award bios diff --git a/src/southbridge/via/vt8231/vt8231_lpc.c b/src/southbridge/via/vt8231/vt8231_lpc.c index cee46b51bb..9799195d87 100644 --- a/src/southbridge/via/vt8231/vt8231_lpc.c +++ b/src/southbridge/via/vt8231/vt8231_lpc.c @@ -23,7 +23,7 @@ static const unsigned char slotIrqs[4] = { 5, 10, 12, 11 }; static void pci_routing_fixup(struct device *dev) { - printk_info("%s: dev is %p\n", __func__, dev); + printk(BIOS_INFO, "%s: dev is %p\n", __func__, dev); if (dev) { /* initialize PCI interupts - these assignments depend on the PCB routing of PINTA-D @@ -39,17 +39,17 @@ static void pci_routing_fixup(struct device *dev) } // Standard southbridge components - printk_info("setting southbridge\n"); + printk(BIOS_INFO, "setting southbridge\n"); pci_assign_irqs(0, 0x11, southbridgeIrqs); // Ethernet built into southbridge - printk_info("setting ethernet\n"); + printk(BIOS_INFO, "setting ethernet\n"); pci_assign_irqs(0, 0x12, enetIrqs); // PCI slot - printk_info("setting pci slot\n"); + printk(BIOS_INFO, "setting pci slot\n"); pci_assign_irqs(0, 0x14, slotIrqs); - printk_info("%s: DONE\n", __func__); + printk(BIOS_INFO, "%s: DONE\n", __func__); } static void vt8231_init(struct device *dev) @@ -57,7 +57,7 @@ static void vt8231_init(struct device *dev) unsigned char enables; struct southbridge_via_vt8231_config *conf = dev->chip_info; - printk_debug("vt8231 init\n"); + printk(BIOS_DEBUG, "vt8231 init\n"); // enable the internal I/O decode enables = pci_read_config8(dev, 0x6C); @@ -102,18 +102,18 @@ static void vt8231_init(struct device *dev) // First do some more things to devfn (17,0) // note: this should already be cleared, according to the book. enables = pci_read_config8(dev, 0x50); - printk_debug("IDE enable in reg. 50 is 0x%x\n", enables); + printk(BIOS_DEBUG, "IDE enable in reg. 50 is 0x%x\n", enables); enables &= ~8; // need manifest constant here! - printk_debug("set IDE reg. 50 to 0x%x\n", enables); + printk(BIOS_DEBUG, "set IDE reg. 50 to 0x%x\n", enables); pci_write_config8(dev, 0x50, enables); // set default interrupt values (IDE) enables = pci_read_config8(dev, 0x4c); - printk_debug("IRQs in reg. 4c are 0x%x\n", enables & 0xf); + printk(BIOS_DEBUG, "IRQs in reg. 4c are 0x%x\n", enables & 0xf); // clear out whatever was there. enables &= ~0xf; enables |= 4; - printk_debug("setting reg. 4c to 0x%x\n", enables); + printk(BIOS_DEBUG, "setting reg. 4c to 0x%x\n", enables); pci_write_config8(dev, 0x4c, enables); // set up the serial port interrupts. diff --git a/src/southbridge/via/vt8231/vt8231_nic.c b/src/southbridge/via/vt8231/vt8231_nic.c index 828cdaf2f6..d4771f6816 100644 --- a/src/southbridge/via/vt8231/vt8231_nic.c +++ b/src/southbridge/via/vt8231/vt8231_nic.c @@ -12,7 +12,7 @@ static void nic_init(struct device *dev) { uint8_t byte; - printk_debug("Configuring VIA LAN\n"); + printk(BIOS_DEBUG, "Configuring VIA LAN\n"); /* We don't need stepping - though the device supports it */ byte = pci_read_config8(dev, PCI_COMMAND); diff --git a/src/southbridge/via/vt8235/vt8235.c b/src/southbridge/via/vt8235/vt8235.c index f384847d5c..228da0f948 100644 --- a/src/southbridge/via/vt8235/vt8235.c +++ b/src/southbridge/via/vt8235/vt8235.c @@ -14,7 +14,7 @@ static int enabled = 0; void hard_reset(void) { - printk_err("NO HARD RESET ON VT8235! FIX ME!\n"); + printk(BIOS_ERR, "NO HARD RESET ON VT8235! FIX ME!\n"); } static void keyboard_on(struct device *dev) @@ -34,11 +34,11 @@ void dump_south(device_t dev0) int i,j; for(i = 0; i < 256; i += 16) { - printk_debug("0x%x: ", i); + printk(BIOS_DEBUG, "0x%x: ", i); for(j = 0; j < 16; j++) { - printk_debug("%02x ", pci_read_config8(dev0, i+j)); + printk(BIOS_DEBUG, "%02x ", pci_read_config8(dev0, i+j)); } - printk_debug("\n"); + printk(BIOS_DEBUG, "\n"); } } @@ -61,7 +61,7 @@ static void vt8235_enable(struct device *dev) vendor = pci_read_config16(dev,0); model = pci_read_config16(dev,0x2); - printk_debug("In vt8235_enable %04x %04x.\n",vendor,model); + printk(BIOS_DEBUG, "In vt8235_enable %04x %04x.\n",vendor,model); /* if this is not the southbridge itself just return */ /* this is necessary because USB devices are slot 10, whereas this device is slot 11 @@ -70,7 +70,7 @@ static void vt8235_enable(struct device *dev) if( (vendor != PCI_VENDOR_ID_VIA) || (model != PCI_DEVICE_ID_VIA_8235)) return; - printk_debug("Initialising Devices\n"); + printk(BIOS_DEBUG, "Initialising Devices\n"); setup_i8259(); // make sure interupt controller is configured before keyboard init diff --git a/src/southbridge/via/vt8235/vt8235_ide.c b/src/southbridge/via/vt8235/vt8235_ide.c index 9c2af3c781..ec22f9053b 100644 --- a/src/southbridge/via/vt8235/vt8235_ide.c +++ b/src/southbridge/via/vt8235/vt8235_ide.c @@ -10,7 +10,7 @@ static void ide_init(struct device *dev) struct southbridge_via_vt8235_config *conf = dev->chip_info; unsigned char enables; - printk_info("Enabling VIA IDE.\n"); + printk(BIOS_INFO, "Enabling VIA IDE.\n"); /*if (!conf->enable_native_ide) { */ /* @@ -18,23 +18,23 @@ static void ide_init(struct device *dev) * use PCI interrupts. Using PCI ints confuses linux for some * reason. */ - printk_info("%s: enabling compatibility IDE addresses\n", + printk(BIOS_INFO, "%s: enabling compatibility IDE addresses\n", __func__); enables = pci_read_config8(dev, 0x42); - printk_debug("enables in reg 0x42 0x%x\n", enables); + printk(BIOS_DEBUG, "enables in reg 0x42 0x%x\n", enables); enables &= ~0xc0; // compatability mode pci_write_config8(dev, 0x42, enables); enables = pci_read_config8(dev, 0x42); - printk_debug("enables in reg 0x42 read back as 0x%x\n", + printk(BIOS_DEBUG, "enables in reg 0x42 read back as 0x%x\n", enables); /* } */ enables = pci_read_config8(dev, 0x40); - printk_debug("enables in reg 0x40 0x%x\n", enables); + printk(BIOS_DEBUG, "enables in reg 0x40 0x%x\n", enables); enables |= 3; pci_write_config8(dev, 0x40, enables); enables = pci_read_config8(dev, 0x40); - printk_debug("enables in reg 0x40 read back as 0x%x\n", enables); + printk(BIOS_DEBUG, "enables in reg 0x40 read back as 0x%x\n", enables); // Enable prefetch buffers enables = pci_read_config8(dev, 0x41); @@ -58,7 +58,7 @@ static void ide_init(struct device *dev) // kevinh@ispiri.com - the standard linux drivers seem ass slow when // used in native mode - I've changed back to classic enables = pci_read_config8(dev, 0x9); - printk_debug("enables in reg 0x9 0x%x\n", enables); + printk(BIOS_DEBUG, "enables in reg 0x9 0x%x\n", enables); // by the book, set the low-order nibble to 0xa. if (conf->enable_native_ide) { enables &= ~0xf; @@ -70,11 +70,11 @@ static void ide_init(struct device *dev) pci_write_config8(dev, 0x9, enables); enables = pci_read_config8(dev, 0x9); - printk_debug("enables in reg 0x9 read back as 0x%x\n", enables); + printk(BIOS_DEBUG, "enables in reg 0x9 read back as 0x%x\n", enables); // standard bios sets master bit. enables = pci_read_config8(dev, 0x4); - printk_debug("command in reg 0x4 0x%x\n", enables); + printk(BIOS_DEBUG, "command in reg 0x4 0x%x\n", enables); enables |= 7; // No need for stepping - kevinh@ispiri.com @@ -82,7 +82,7 @@ static void ide_init(struct device *dev) pci_write_config8(dev, 0x4, enables); enables = pci_read_config8(dev, 0x4); - printk_debug("command in reg 0x4 reads back as 0x%x\n", enables); + printk(BIOS_DEBUG, "command in reg 0x4 reads back as 0x%x\n", enables); if (!conf->enable_native_ide) { // Use compatability mode - per award bios diff --git a/src/southbridge/via/vt8235/vt8235_lpc.c b/src/southbridge/via/vt8235/vt8235_lpc.c index 052c4c9415..92ba973661 100644 --- a/src/southbridge/via/vt8235/vt8235_lpc.c +++ b/src/southbridge/via/vt8235/vt8235_lpc.c @@ -56,7 +56,7 @@ static unsigned char *pin_to_irq(const unsigned char *pin) static void pci_routing_fixup(struct device *dev) { - printk_info("%s: dev is %p\n", __func__, dev); + printk(BIOS_INFO, "%s: dev is %p\n", __func__, dev); /* set up PCI IRQ routing */ pci_write_config8(dev, 0x55, pciIrqs[0] << 4); @@ -65,38 +65,38 @@ static void pci_routing_fixup(struct device *dev) // firewire built into southbridge - printk_info("setting firewire\n"); + printk(BIOS_INFO, "setting firewire\n"); pci_assign_irqs(0, 0x0d, pin_to_irq(firewirePins)); // Standard usb components - printk_info("setting usb\n"); + printk(BIOS_INFO, "setting usb\n"); pci_assign_irqs(0, 0x10, pin_to_irq(usbPins)); // VT8235 + sound hardware - printk_info("setting vt8235\n"); + printk(BIOS_INFO, "setting vt8235\n"); pci_assign_irqs(0, 0x11, pin_to_irq(vt8235Pins)); // Ethernet built into southbridge - printk_info("setting ethernet\n"); + printk(BIOS_INFO, "setting ethernet\n"); pci_assign_irqs(0, 0x12, pin_to_irq(enetPins)); // VGA - printk_info("setting vga\n"); + printk(BIOS_INFO, "setting vga\n"); pci_assign_irqs(1, 0x00, pin_to_irq(vgaPins)); // PCI slot - printk_info("setting pci slot\n"); + printk(BIOS_INFO, "setting pci slot\n"); pci_assign_irqs(0, 0x14, pin_to_irq(slotPins)); // Cardbus slot - printk_info("setting cardbus slot\n"); + printk(BIOS_INFO, "setting cardbus slot\n"); pci_assign_irqs(0, 0x0a, pin_to_irq(cbPins)); // Via 2 slot riser card 2nd slot - printk_info("setting riser slot\n"); + printk(BIOS_INFO, "setting riser slot\n"); pci_assign_irqs(0, 0x13, pin_to_irq(riserPins)); - printk_spew("%s: DONE\n", __func__); + printk(BIOS_SPEW, "%s: DONE\n", __func__); } /* @@ -154,7 +154,7 @@ static void vt8235_init(struct device *dev) { unsigned char enables; - printk_debug("vt8235 init\n"); + printk(BIOS_DEBUG, "vt8235 init\n"); // enable the internal I/O decode enables = pci_read_config8(dev, 0x6C); diff --git a/src/southbridge/via/vt8235/vt8235_nic.c b/src/southbridge/via/vt8235/vt8235_nic.c index 09ea17e078..86fef895de 100644 --- a/src/southbridge/via/vt8235/vt8235_nic.c +++ b/src/southbridge/via/vt8235/vt8235_nic.c @@ -12,7 +12,7 @@ static void nic_init(struct device *dev) { uint8_t byte; - printk_debug("Configuring VIA Rhine LAN\n"); + printk(BIOS_DEBUG, "Configuring VIA Rhine LAN\n"); /* We don't need stepping - though the device supports it */ byte = pci_read_config8(dev, PCI_COMMAND); diff --git a/src/southbridge/via/vt8235/vt8235_usb.c b/src/southbridge/via/vt8235/vt8235_usb.c index 2318465058..8b2a685807 100644 --- a/src/southbridge/via/vt8235/vt8235_usb.c +++ b/src/southbridge/via/vt8235/vt8235_usb.c @@ -9,7 +9,7 @@ static void usb_init(struct device *dev) { - printk_debug("Configuring VIA USB 1.1\n"); + printk(BIOS_DEBUG, "Configuring VIA USB 1.1\n"); /* pci_write_config8(dev, 0x04, 0x07); */ diff --git a/src/southbridge/via/vt8237r/vt8237r.c b/src/southbridge/via/vt8237r/vt8237r.c index 8be26db608..2b5d34bccc 100644 --- a/src/southbridge/via/vt8237r/vt8237r.c +++ b/src/southbridge/via/vt8237r/vt8237r.c @@ -30,7 +30,7 @@ void hard_reset(void) { - printk_err("NO HARD RESET ON VT8237R! FIX ME!\n"); + printk(BIOS_ERR, "NO HARD RESET ON VT8237R! FIX ME!\n"); } #if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 7 @@ -61,10 +61,10 @@ void dump_south(device_t dev) int i, j; for (i = 0; i < 256; i += 16) { - printk_debug("%02x: ", i); + printk(BIOS_DEBUG, "%02x: ", i); for (j = 0; j < 16; j++) - printk_debug("%02x ", pci_read_config8(dev, i + j)); - printk_debug("\n"); + printk(BIOS_DEBUG, "%02x ", pci_read_config8(dev, i + j)); + printk(BIOS_DEBUG, "\n"); } } diff --git a/src/southbridge/via/vt8237r/vt8237r_ide.c b/src/southbridge/via/vt8237r/vt8237r_ide.c index 86a87ac791..0b4dccc2f0 100644 --- a/src/southbridge/via/vt8237r/vt8237r_ide.c +++ b/src/southbridge/via/vt8237r/vt8237r_ide.c @@ -40,15 +40,15 @@ static void ide_init(struct device *dev) device_t lpc_dev; int i, j; - printk_info("%s IDE interface %s\n", "Primary", + printk(BIOS_INFO, "%s IDE interface %s\n", "Primary", sb->ide0_enable ? "enabled" : "disabled"); - printk_info("%s IDE interface %s\n", "Secondary", + printk(BIOS_INFO, "%s IDE interface %s\n", "Secondary", sb->ide1_enable ? "enabled" : "disabled"); enables = pci_read_config8(dev, IDE_CS) & ~0x3; enables |= (sb->ide0_enable << 1) | sb->ide1_enable; pci_write_config8(dev, IDE_CS, enables); enables = pci_read_config8(dev, IDE_CS); - printk_debug("Enables in reg 0x40 read back as 0x%x\n", enables); + printk(BIOS_DEBUG, "Enables in reg 0x40 read back as 0x%x\n", enables); /* Enable only compatibility mode. */ enables = pci_read_config8(dev, 0x09); @@ -59,7 +59,7 @@ static void ide_init(struct device *dev) enables &= ~0xc0; pci_write_config8(dev, IDE_CONF_II, enables); enables = pci_read_config8(dev, IDE_CONF_II); - printk_debug("Enables in reg 0x42 read back as 0x%x\n", enables); + printk(BIOS_DEBUG, "Enables in reg 0x42 read back as 0x%x\n", enables); /* Enable prefetch buffers. */ enables = pci_read_config8(dev, IDE_CONF_I); diff --git a/src/southbridge/via/vt8237r/vt8237r_lpc.c b/src/southbridge/via/vt8237r/vt8237r_lpc.c index d53028128f..4e09823a69 100644 --- a/src/southbridge/via/vt8237r/vt8237r_lpc.c +++ b/src/southbridge/via/vt8237r/vt8237r_lpc.c @@ -238,7 +238,7 @@ static void setup_pm(device_t dev) tmp = inw(VT8237R_ACPI_IO_BASE + 0x04); #if CONFIG_HAVE_ACPI_RESUME == 1 acpi_slp_type = ((tmp & (7 << 10)) >> 10) == 1 ? 3 : 0 ; - printk_debug("SLP_TYP type was %x %x\n", tmp, acpi_slp_type); + printk(BIOS_DEBUG, "SLP_TYP type was %x %x\n", tmp, acpi_slp_type); #endif /* clear sleep */ tmp &= ~(7 << 10); @@ -251,7 +251,7 @@ static void vt8237r_init(struct device *dev) u8 enables, reg8; #if CONFIG_EPIA_VT8237R_INIT - printk_spew("Entering vt8237r_init, for EPIA.\n"); + printk(BIOS_SPEW, "Entering vt8237r_init, for EPIA.\n"); /* * TODO: Looks like stock BIOS can do this but causes a hang * Enable SATA LED, disable special CPU Frequency Change - @@ -277,7 +277,7 @@ static void vt8237r_init(struct device *dev) pci_write_config8(dev, 0x4E, enables); #else - printk_spew("Entering vt8237r_init.\n"); + printk(BIOS_SPEW, "Entering vt8237r_init.\n"); /* * Enable SATA LED, disable special CPU Frequency Change - * GPIO28 GPIO22 GPIO29 GPIO23 are GPIOs. @@ -318,7 +318,7 @@ static void vt8237r_init(struct device *dev) outb(0x1, VT8237R_ACPI_IO_BASE + 0x11); #endif - printk_spew("Leaving %s.\n", __func__); + printk(BIOS_SPEW, "Leaving %s.\n", __func__); } static void vt8237s_init(struct device *dev) diff --git a/src/southbridge/via/vt8237r/vt8237r_sata.c b/src/southbridge/via/vt8237r/vt8237r_sata.c index b0c58aa9c1..8d09057f27 100644 --- a/src/southbridge/via/vt8237r/vt8237r_sata.c +++ b/src/southbridge/via/vt8237r/vt8237r_sata.c @@ -28,7 +28,7 @@ static void sata_i_init(struct device *dev) { u8 reg; - printk_debug("Configuring VIA SATA controller\n"); + printk(BIOS_DEBUG, "Configuring VIA SATA controller\n"); /* Class IDE Disk */ reg = pci_read_config8(dev, SATA_MISC_CTRL); diff --git a/src/southbridge/via/vt8237r/vt8237r_usb.c b/src/southbridge/via/vt8237r/vt8237r_usb.c index 2c554ca3da..4bd33d6346 100644 --- a/src/southbridge/via/vt8237r/vt8237r_usb.c +++ b/src/southbridge/via/vt8237r/vt8237r_usb.c @@ -34,16 +34,16 @@ static void usb_i_init(struct device *dev) #if CONFIG_EPIA_VT8237R_INIT u8 reg8; - printk_debug("Entering %s\n", __func__); + printk(BIOS_DEBUG, "Entering %s\n", __func__); - printk_spew("%s Read %02X from PCI Command Reg\n", dev_path(dev), reg8); + printk(BIOS_SPEW, "%s Read %02X from PCI Command Reg\n", dev_path(dev), reg8); reg8 = pci_read_config8(dev, 0x04); reg8 = reg8 | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; pci_write_config8(dev, 0x04, reg8); - printk_spew("%s Wrote %02X to PCI Command Reg\n", dev_path(dev), reg8); + printk(BIOS_SPEW, "%s Wrote %02X to PCI Command Reg\n", dev_path(dev), reg8); /* Set Cache Line Size and Latency Timer */ pci_write_config8(dev, 0x0c, 0x08); @@ -74,7 +74,7 @@ static void vt8237_usb_i_read_resources(struct device *dev) struct resource *res; u8 function = (u8) dev->path.pci.devfn & 0x7; - printk_spew("VT8237R Fixing USB 1.1 fn %d I/O resource = 0x%04X\n", function, usb_io_addr[function]); + printk(BIOS_SPEW, "VT8237R Fixing USB 1.1 fn %d I/O resource = 0x%04X\n", function, usb_io_addr[function]); /* Fix the I/O Resources of the USB1.1 Interfaces */ /* Auto PCI probe seems to size the resources */ @@ -98,7 +98,7 @@ static void usb_ii_init(struct device *dev) #if CONFIG_EPIA_VT8237R_INIT u8 reg8; - printk_debug("Entering %s\n", __func__); + printk(BIOS_DEBUG, "Entering %s\n", __func__); /* Set memory Write and Invalidate */ reg8 = pci_read_config8(dev, 0x04); |