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authorRonald G. Minnich <rminnich@gmail.com>2006-04-25 19:57:39 +0000
committerRonald G. Minnich <rminnich@gmail.com>2006-04-25 19:57:39 +0000
commitcf120d1a89e81b3bb3c4a201a759054ccc006919 (patch)
tree93e6d2248e234463eb12a4a9aa04c20c27ecc721 /src/southbridge
parent1c2f49e74aa254c7c415641002c0c2f52ed42a5c (diff)
downloadcoreboot-cf120d1a89e81b3bb3c4a201a759054ccc006919.tar.xz
builds and should do the right things for sb for interrupt routing.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2277 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge')
-rw-r--r--src/southbridge/amd/cs5536/Config.lb2
-rw-r--r--src/southbridge/amd/cs5536/cs5536.c30
2 files changed, 22 insertions, 10 deletions
diff --git a/src/southbridge/amd/cs5536/Config.lb b/src/southbridge/amd/cs5536/Config.lb
index 36b0f97e7a..618db33f4f 100644
--- a/src/southbridge/amd/cs5536/Config.lb
+++ b/src/southbridge/amd/cs5536/Config.lb
@@ -1,4 +1,4 @@
-#config chip.h
+config chip.h
driver cs5536.o
#driver cs5536_pci.o
#driver cs5536_ide.o
diff --git a/src/southbridge/amd/cs5536/cs5536.c b/src/southbridge/amd/cs5536/cs5536.c
index 90ffe323ec..37c54d5c50 100644
--- a/src/southbridge/amd/cs5536/cs5536.c
+++ b/src/southbridge/amd/cs5536/cs5536.c
@@ -5,7 +5,9 @@
#include <device/pci_ops.h>
#include <device/pci_ids.h>
#include <console/console.h>
-#include "cs5536.h"
+#include <cpu/amd/gx2def.h>
+#include <cpu/x86/msr.h>
+#include "chip.h"
static void southbridge_init(struct device *dev)
{
@@ -17,23 +19,25 @@ static void southbridge_enable(struct device *dev)
{
struct southbridge_amd_cs5536_config *sb = (struct southbridge_amd_cs5536_config *)dev->chip_info;
msr_t msr;
- struct device *gpiodev;
- unsigned short gpiobase = MDD_GPIO;
+ /*
+ * struct device *gpiodev;
+ * unsigned short gpiobase = MDD_GPIO;
+ */
printk_err("%s: dev is %p\n", __FUNCTION__, dev);
- if (chip_info->lpc_serirq_enable) {
- msr.lo = chip_info->lpc_serirq_enable;
+ if (sb->lpc_serirq_enable) {
+ msr.lo = sb->lpc_serirq_enable;
msr.hi = 0;
wrmsr(MDD_LPC_SIRQ, msr);
}
- if (chip_info->lpc_irq) {
- msr.lo = chip_info->lpc_irq;
+ if (sb->lpc_irq) {
+ msr.lo = sb->lpc_irq;
msr.hi = 0;
wrmsr(MDD_IRQM_LPC, msr);
}
- if (chip_info->enable_gpio0_inta){
- rdmsr(MDD_IRQM_ZHIGH, msr);
+ if (sb->enable_gpio0_inta){
+ msr = rdmsr(MDD_IRQM_ZHIGH);
msr.lo |= 0x10;
wrmsr(MDD_IRQM_ZHIGH, msr);
/* todo: look the device up. But we know that gpiobase is 0x6100 */
@@ -69,3 +73,11 @@ static struct pci_driver cs5536_pci_driver __pci_driver = {
.vendor = PCI_VENDOR_ID_AMD,
.device = PCI_DEVICE_ID_AMD_CS5536_ISA
};
+
+struct chip_operations southbridge_amd_cs5536_ops = {
+ CHIP_NAME("AMD cs5536")
+ /* This only called when this device is listed in the
+ * static device tree.
+ */
+ .enable_dev = southbridge_enable,
+};