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authorIdwer Vollering <vidwer@gmail.com>2013-12-22 21:38:18 +0000
committerAlexandru Gagniuc <mr.nuke.me@gmail.com>2013-12-23 02:12:51 +0100
commitd26da9c8f0794f473f476a69821abffb52996237 (patch)
tree210ccdfcf6b24b7bc6971aaec964878338c5d2dc /src/southbridge
parentc6c8cb7f799f81a55b94c1e64ee13773dfc7f631 (diff)
downloadcoreboot-d26da9c8f0794f473f476a69821abffb52996237.tar.xz
Coding style: punctuation cleanup [1/2].
Clean up superfluous line terminators. Change-Id: If837b4f1b3e7702cbb09ba12f53ed788a8f31386 Signed-off-by: Idwer Vollering <vidwer@gmail.com> Reviewed-on: http://review.coreboot.org/4562 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/southbridge')
-rw-r--r--src/southbridge/amd/cimx/sb800/spi.c2
-rw-r--r--src/southbridge/amd/sb700/sm.c2
-rw-r--r--src/southbridge/amd/sb800/early_setup.c2
-rw-r--r--src/southbridge/intel/i82371eb/fadt.c2
-rw-r--r--src/southbridge/nvidia/mcp55/fadt.c2
-rw-r--r--src/southbridge/via/vt8237r/fadt.c2
6 files changed, 6 insertions, 6 deletions
diff --git a/src/southbridge/amd/cimx/sb800/spi.c b/src/southbridge/amd/cimx/sb800/spi.c
index d85a515fcc..3b2f5562cc 100644
--- a/src/southbridge/amd/cimx/sb800/spi.c
+++ b/src/southbridge/amd/cimx/sb800/spi.c
@@ -117,7 +117,7 @@ static void ImcSleep(void)
static void ImcWakeup(void)
{
u8 cmd_val = 0x96; /* Kick off IMC Mailbox command 96 */
- u8 reg0_val = 0;; /* clear response register */
+ u8 reg0_val = 0; /* clear response register */
u8 reg1_val = 0xB5; /* release ownership flag */
WriteECmsg (MSG_REG0, AccWidthUint8, &reg0_val);
diff --git a/src/southbridge/amd/sb700/sm.c b/src/southbridge/amd/sb700/sm.c
index 2c2f6d53f6..0fb6556f37 100644
--- a/src/southbridge/amd/sb700/sm.c
+++ b/src/southbridge/amd/sb700/sm.c
@@ -151,7 +151,7 @@ static void sm_init(device_t dev)
pm_iowrite(0x55, byte);
byte = pm_ioread(0xD7);
- byte |= 1 << 6 | 1 << 1;;
+ byte |= 1 << 6 | 1 << 1;
pm_iowrite(0xD7, byte);
/* 2.15 */
diff --git a/src/southbridge/amd/sb800/early_setup.c b/src/southbridge/amd/sb800/early_setup.c
index b3d16bf173..213cae96e7 100644
--- a/src/southbridge/amd/sb800/early_setup.c
+++ b/src/southbridge/amd/sb800/early_setup.c
@@ -276,7 +276,7 @@ void sb800_pci_port80(void)
pci_write_config8(dev, 0x04, byte);
/* LPC controller */
- dev = PCI_DEV(0, 0x14, 3);;//pci_locate_device(PCI_ID(0x1002, 0x439D), 0);
+ dev = PCI_DEV(0, 0x14, 3);//pci_locate_device(PCI_ID(0x1002, 0x439D), 0);
byte = pci_read_config8(dev, 0x4A);
byte &= ~(1 << 5); /* disable lpc port 80 */
diff --git a/src/southbridge/intel/i82371eb/fadt.c b/src/southbridge/intel/i82371eb/fadt.c
index e4c82084ca..09874f71ad 100644
--- a/src/southbridge/intel/i82371eb/fadt.c
+++ b/src/southbridge/intel/i82371eb/fadt.c
@@ -212,7 +212,7 @@ void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt)
fadt->x_gpe0_blk.addrh = 0x0;
fadt->x_gpe1_blk.space_id = 1;
- fadt->x_gpe1_blk.bit_width = fadt->gpe1_blk_len * 8;;
+ fadt->x_gpe1_blk.bit_width = fadt->gpe1_blk_len * 8;
fadt->x_gpe1_blk.bit_offset = 0;
fadt->x_gpe1_blk.resv = 0;
fadt->x_gpe1_blk.addrl = fadt->gpe1_blk;
diff --git a/src/southbridge/nvidia/mcp55/fadt.c b/src/southbridge/nvidia/mcp55/fadt.c
index f9ac8ee1e6..68f03e0a9c 100644
--- a/src/southbridge/nvidia/mcp55/fadt.c
+++ b/src/southbridge/nvidia/mcp55/fadt.c
@@ -163,7 +163,7 @@ void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt)
fadt->x_gpe0_blk.addrh = 0x0;
fadt->x_gpe1_blk.space_id = 1;
- fadt->x_gpe1_blk.bit_width = fadt->gpe1_blk_len * 8;;
+ fadt->x_gpe1_blk.bit_width = fadt->gpe1_blk_len * 8;
fadt->x_gpe1_blk.bit_offset = 0;
fadt->x_gpe1_blk.resv = 0;
fadt->x_gpe1_blk.addrl = fadt->gpe1_blk;
diff --git a/src/southbridge/via/vt8237r/fadt.c b/src/southbridge/via/vt8237r/fadt.c
index 5b3bc5608b..ecd81b38ba 100644
--- a/src/southbridge/via/vt8237r/fadt.c
+++ b/src/southbridge/via/vt8237r/fadt.c
@@ -163,7 +163,7 @@ void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt)
fadt->x_gpe0_blk.addrh = 0x0;
fadt->x_gpe1_blk.space_id = 1;
- fadt->x_gpe1_blk.bit_width = fadt->gpe1_blk_len * 8;;
+ fadt->x_gpe1_blk.bit_width = fadt->gpe1_blk_len * 8;
fadt->x_gpe1_blk.bit_offset = 0;
fadt->x_gpe1_blk.resv = 0;
fadt->x_gpe1_blk.addrl = fadt->gpe1_blk;