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authorVladimir Serbinenko <phcoder@gmail.com>2014-08-31 02:21:43 +0200
committerVladimir Serbinenko <phcoder@gmail.com>2014-10-18 22:01:18 +0200
commite6e5b5ef556904ab5d03f7b6f750b4d25df961f4 (patch)
tree84571fcac8a08f3f031ce21064f5d4e109eeeee7 /src/southbridge
parent2fc0a1d457901171cc226390925f0a6320821549 (diff)
downloadcoreboot-e6e5b5ef556904ab5d03f7b6f750b4d25df961f4.tar.xz
sch: Switch to per-device ACPI
Change-Id: I4cf0a67b0251d2d3adff5de74bf56b7d4c4524ee Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6811 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/southbridge')
-rw-r--r--src/southbridge/intel/sch/acpi/globalnvs.asl4
-rw-r--r--src/southbridge/intel/sch/lpc.c26
-rw-r--r--src/southbridge/intel/sch/nvs.h2
3 files changed, 30 insertions, 2 deletions
diff --git a/src/southbridge/intel/sch/acpi/globalnvs.asl b/src/southbridge/intel/sch/acpi/globalnvs.asl
index 5ac1c83cd6..7db71f96ac 100644
--- a/src/southbridge/intel/sch/acpi/globalnvs.asl
+++ b/src/southbridge/intel/sch/acpi/globalnvs.asl
@@ -30,8 +30,8 @@ Name(\DSEN, 1) // Display Output Switching Enable
* we have to fix it up in coreboot's ACPI creation phase.
*/
-
-OperationRegion (GNVS, SystemMemory, 0xC0DEBABE, 0x100)
+External(NVSA)
+OperationRegion (GNVS, SystemMemory, NVSA, 0x100)
Field (GNVS, ByteAcc, NoLock, Preserve)
{
/* Miscellaneous */
diff --git a/src/southbridge/intel/sch/lpc.c b/src/southbridge/intel/sch/lpc.c
index 08f41627d4..7d209b1cc5 100644
--- a/src/southbridge/intel/sch/lpc.c
+++ b/src/southbridge/intel/sch/lpc.c
@@ -24,6 +24,12 @@
#include <device/pci_ids.h>
#include <arch/io.h>
#include <arch/ioapic.h>
+#include <arch/acpigen.h>
+#include <arch/acpigen.h>
+#include <cpu/cpu.h>
+#include <cbmem.h>
+#include <string.h>
+#include "nvs.h"
#include "chip.h"
/* SCH LPC defines */
@@ -182,6 +188,24 @@ static void set_subsystem(device_t dev, unsigned vendor, unsigned device)
}
}
+static void southbridge_inject_dsdt(void)
+{
+ global_nvs_t *gnvs = cbmem_add (CBMEM_ID_ACPI_GNVS, sizeof (*gnvs));
+
+ if (gnvs) {
+ int scopelen;
+ memset(gnvs, 0, sizeof(*gnvs));
+ acpi_create_gnvs(gnvs);
+ /* And tell SMI about it */
+ smm_setup_structures(gnvs, NULL, NULL);
+
+ /* Add it to SSDT. */
+ scopelen = acpigen_write_scope("\\");
+ scopelen += acpigen_write_name_dword("NVSA", (u32) gnvs);
+ acpigen_patch_len(scopelen - 1);
+ }
+}
+
static struct pci_operations pci_ops = {
.set_subsystem = set_subsystem,
};
@@ -190,6 +214,8 @@ static struct device_operations device_ops = {
.read_resources = sch_lpc_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
+ .acpi_inject_dsdt_generator = southbridge_inject_dsdt,
+ .write_acpi_tables = acpi_write_hpet,
.init = lpc_init,
.scan_bus = scan_static_bus,
.ops_pci = &pci_ops,
diff --git a/src/southbridge/intel/sch/nvs.h b/src/southbridge/intel/sch/nvs.h
index 14f0ad36c1..c987d92beb 100644
--- a/src/southbridge/intel/sch/nvs.h
+++ b/src/southbridge/intel/sch/nvs.h
@@ -135,3 +135,5 @@ typedef struct {
u8 bten;
u8 rsvd13[14];
} __attribute__((packed)) global_nvs_t;
+
+void acpi_create_gnvs(global_nvs_t * gnvs);