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| author | Kimarie Hoot <kimarie.hoot@se-eng.com> | 2012-07-14 08:26:08 -0600 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2012-07-25 19:52:07 +0200 |
| commit | e6f459ca4b24d0f6dc07c2dd6a5278543c0c745d (patch) | |
| tree | e3d4296fefe809a0ca7b401305b4068441ac7e39 /src/southbridge | |
| parent | ac3aa096c9c2845cfcab7f7fbe50cc56f92a7264 (diff) | |
| download | coreboot-e6f459ca4b24d0f6dc07c2dd6a5278543c0c745d.tar.xz | |
CougarPoint/PantherPoint: Add HM77 device ID to table
Change-Id: Ic5aada423d8e61abbebfcaaf5cb02ede80dfae02
Signed-off-by: Kimarie Hoot <kimarie.hoot@se-eng.com>
Reviewed-on: http://review.coreboot.org/1339
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/southbridge')
| -rw-r--r-- | src/southbridge/intel/bd82x6x/lpc.c | 9 |
1 files changed, 4 insertions, 5 deletions
diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index 30edbde6eb..5f81edf394 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -653,16 +653,15 @@ static struct device_operations device_ops = { }; -/* IDs for LPC device of Intel 6 series Chipset and - * Intel C200 Series Chipset according to specification - * update from August 2011 +/* IDs for LPC device of Intel 6 Series Chipset, Intel 7 Series Chipset, and + * Intel C200 Series Chipset */ static const unsigned short pci_device_ids[] = { 0x1c46, 0x1c47, 0x1c49, 0x1c4a, 0x1c4b, 0x1c4c, 0x1c4d, 0x1c4e, 0x1c4f, 0x1c50, 0x1c52, 0x1c54, - 0x1e55, 0x1c56, 0x1c5c, 0x1e5d, - 0x1e5e, 0x1e5f, + 0x1e55, 0x1c56, 0x1e57, 0x1c5c, + 0x1e5d, 0x1e5e, 0x1e5f, 0 }; static const struct pci_driver pch_lpc __pci_driver = { |