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| author | Edward O'Callaghan <eocallaghan@alterapraxis.com> | 2014-08-02 10:15:44 +1000 |
|---|---|---|
| committer | Edward O'Callaghan <eocallaghan@alterapraxis.com> | 2014-08-13 05:01:58 +0200 |
| commit | ef3a17bd88f3c751ef98d3be94eb922da14ce3c5 (patch) | |
| tree | add50fba9f74cc92e6fc66c94c64a23186f885f9 /src/southbridge | |
| parent | 691ff08e27b9f79e5178a0c3e6c51f9327f207d5 (diff) | |
| download | coreboot-ef3a17bd88f3c751ef98d3be94eb922da14ce3c5.tar.xz | |
util/inteltool: Typo in dump output for 'GP_IO_SEL3'
The GPIO offset of '0x44 - GP_IO_SEL3' as specified in the pch.h header
is incorrectly reported as 'GPIO_SEL3'.
Change-Id: I56dcdda109d5f57ed45938d60b995807bdfb46b1
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6459
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/southbridge')
0 files changed, 0 insertions, 0 deletions