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authorDavid Hendricks <dhendrix@chromium.org>2014-04-13 16:27:02 -0700
committerMarc Jones <marc.jones@se-eng.com>2014-12-17 20:50:33 +0100
commitf2612a10610e7a890badb4588c0ceb2d92ff9281 (patch)
tree41d8bb0c5d4c3f83330db73549fd6114a70cc44c /src/southbridge
parent229ad270f67af53c62b1ef6fe74bc48ef3d1ec58 (diff)
downloadcoreboot-f2612a10610e7a890badb4588c0ceb2d92ff9281.tar.xz
x86: Initialize SPI controller explicitly during PCH init
This ensures that SPI is ready when eventlog code is used. x86 platforms which use eventlog invoke elog_clear() in GSMI and elog_add_event_raw() when deciding the boot path based on ME status. For the SMM case spi_init() is called during the finalize stage in SMM setup. For the boot path case we can call spi_init() at the beginning of BS_DEV_INIT and it will be ready to use when the boot path is determined from the ME status. BUG=none BRANCH=none TEST=tested on Link (bd82x6x), Beltino (Lynxpoint), and Rambi (Baytrail) with follow-up patch Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Change-Id: Id3aef0fc7d4df5aaa3c1c2c2383b339430e7a6a1 Original-Reviewed-on: https://chromium-review.googlesource.com/194525 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Original-Commit-Queue: David Hendricks <dhendrix@chromium.org> Original-Tested-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit 173d8f08e867bab8c97a6c733580917f5892a45d) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ifaed677bbb141377b36bd9910b2b1c3402654aad Reviewed-on: http://review.coreboot.org/7756 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
Diffstat (limited to 'src/southbridge')
-rw-r--r--src/southbridge/intel/common/spi.c9
1 files changed, 9 insertions, 0 deletions
diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c
index 48c72b7737..3f22bc736f 100644
--- a/src/southbridge/intel/common/spi.c
+++ b/src/southbridge/intel/common/spi.c
@@ -26,6 +26,7 @@
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
+#include <bootstate.h>
#include <delay.h>
#include <arch/io.h>
#include <console/console.h>
@@ -359,6 +360,14 @@ void spi_init(void)
bios_cntl &= ~(1 << 5);
pci_write_config_byte(dev, 0xdc, bios_cntl | 0x1);
}
+static void spi_init_cb(void *unused)
+{
+ spi_init();
+}
+
+BOOT_STATE_INIT_ENTRIES(spi_init_bscb) = {
+ BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, spi_init_cb, NULL),
+};
int spi_claim_bus(struct spi_slave *slave)
{