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authorStefan Reinauer <stepan@coresystems.de>2008-01-18 15:08:58 +0000
committerStefan Reinauer <stepan@openbios.org>2008-01-18 15:08:58 +0000
commitf8ee1806ac524bc782c93eccc59ee3c929abddb9 (patch)
tree7daab6b3aa82476a10d38fbf68068f4a409d2ce9 /src/southbridge
parent7e61e45402aba2b90997f4f02ca8266cf65a229a (diff)
downloadcoreboot-f8ee1806ac524bc782c93eccc59ee3c929abddb9.tar.xz
Rename almost all occurences of LinuxBIOS to coreboot.
Due to the automatic nature of this update, I am self-acking. It worked in abuild. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3053 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge')
-rw-r--r--src/southbridge/amd/cs5530/cs5530_vga.c2
-rw-r--r--src/southbridge/amd/cs5536/cs5536.c2
-rw-r--r--src/southbridge/broadcom/bcm5785/bcm5785_early_setup.c2
-rw-r--r--src/southbridge/intel/i82801ca/i82801ca_early_smbus.c2
-rw-r--r--src/southbridge/ricoh/rl5c476/rl5c476.c2
5 files changed, 5 insertions, 5 deletions
diff --git a/src/southbridge/amd/cs5530/cs5530_vga.c b/src/southbridge/amd/cs5530/cs5530_vga.c
index d60ce6ed6e..2dc8cf0b3b 100644
--- a/src/southbridge/amd/cs5530/cs5530_vga.c
+++ b/src/southbridge/amd/cs5530/cs5530_vga.c
@@ -448,7 +448,7 @@ static void show_boot_splash_16(u32 swidth, u32 sheight, u32 pitch,void *base)
#endif
/**
- * LinuxBIOS management part
+ * coreboot management part
* @param[in] dev Info about the PCI device to initialise
*/
static void cs5530_vga_init(device_t dev)
diff --git a/src/southbridge/amd/cs5536/cs5536.c b/src/southbridge/amd/cs5536/cs5536.c
index 85d086a656..5c827f275f 100644
--- a/src/southbridge/amd/cs5536/cs5536.c
+++ b/src/southbridge/amd/cs5536/cs5536.c
@@ -511,7 +511,7 @@ void chipsetinit(void)
post_code(P80_CHIPSET_INIT);
- /* we hope NEVER to be in linuxbios when S3 resumes
+ /* we hope NEVER to be in coreboot when S3 resumes
if (! IsS3Resume()) */
{
struct acpiinit *aci = acpi_init_table;
diff --git a/src/southbridge/broadcom/bcm5785/bcm5785_early_setup.c b/src/southbridge/broadcom/bcm5785/bcm5785_early_setup.c
index 8167691dea..dd11810483 100644
--- a/src/southbridge/broadcom/bcm5785/bcm5785_early_setup.c
+++ b/src/southbridge/broadcom/bcm5785/bcm5785_early_setup.c
@@ -185,7 +185,7 @@ static void bcm5785_early_setup(void)
byte |= (1<<0); // SATA enable
pci_write_config8(dev, 0x84, byte);
-// wdt and cf9 for later in linuxbios_ram to call hard_reset
+// wdt and cf9 for later in coreboot_ram to call hard_reset
bcm5785_enable_wdt_port_cf9();
bcm5785_enable_msg();
diff --git a/src/southbridge/intel/i82801ca/i82801ca_early_smbus.c b/src/southbridge/intel/i82801ca/i82801ca_early_smbus.c
index c97dd63e2c..8d80135d5d 100644
--- a/src/southbridge/intel/i82801ca/i82801ca_early_smbus.c
+++ b/src/southbridge/intel/i82801ca/i82801ca_early_smbus.c
@@ -28,7 +28,7 @@ static inline void smbus_delay(void)
outb(0x80, 0x80);
}
-// See http://openbios.org/pipermail/linuxbios/2004-September/009077.html
+// See http://www.coreboot.org/pipermail/linuxbios/2004-September/009077.html
// for a description of this function.
static int smbus_wait_until_active(void)
{
diff --git a/src/southbridge/ricoh/rl5c476/rl5c476.c b/src/southbridge/ricoh/rl5c476/rl5c476.c
index f3f4f1c947..b0f4de7e34 100644
--- a/src/southbridge/ricoh/rl5c476/rl5c476.c
+++ b/src/southbridge/ricoh/rl5c476/rl5c476.c
@@ -18,7 +18,7 @@
* MA 02110-1301 USA
*/
/* (C) Copyright 2005 Nick Barker <nick.barker@btinternet.com
- brought into line with the current architecture of LinuxBios */
+ brought into line with the current architecture of coreboot */
#include <arch/io.h>