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authorEdward O'Callaghan <eocallaghan@alterapraxis.com>2014-12-08 04:41:39 +1100
committerEdward O'Callaghan <eocallaghan@alterapraxis.com>2014-12-07 21:11:58 +0100
commitfc3643f326097ae9efd0f6cf7203c6ee61624b1c (patch)
tree9e478d2fe029bd9bbbb53692eb71432845b43ee8 /src/southbridge
parent318e481e55e807d5f1218c28036c6a44f25adee3 (diff)
downloadcoreboot-fc3643f326097ae9efd0f6cf7203c6ee61624b1c.tar.xz
southbridge/dmp/vortex86ex/southbridge.c: Silence bitwise op warns
Silence some useless Clang warns in this case. Change-Id: I202a85f7dec52c65d80e2bc56f7d9e4eb3e61d48 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7696 Tested-by: build bot (Jenkins) Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
Diffstat (limited to 'src/southbridge')
-rw-r--r--src/southbridge/dmp/vortex86ex/southbridge.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/src/southbridge/dmp/vortex86ex/southbridge.c b/src/southbridge/dmp/vortex86ex/southbridge.c
index d4f263bab1..2fe1bc2979 100644
--- a/src/southbridge/dmp/vortex86ex/southbridge.c
+++ b/src/southbridge/dmp/vortex86ex/southbridge.c
@@ -227,11 +227,11 @@ static void pci_routing_fixup(struct device *dev)
unsigned char irqs[4] = { MAC_IRQ, 0, 0, 0 };
pci_assign_irqs(0, 0x8, irqs);
}
- if (OHCII_IRQ && EHCII_IRQ) {
+ if ((OHCII_IRQ != 0) && (EHCII_IRQ != 0)) {
unsigned char irqs[4] = { OHCII_IRQ, EHCII_IRQ, 0, 0 };
pci_assign_irqs(0, 0xa, irqs);
}
- if (CONFIG_IDE_NATIVE_MODE && PIDE_IRQ) {
+ if ((CONFIG_IDE_NATIVE_MODE != 0) && (PIDE_IRQ != 0)) {
/* IDE in native mode, setup PCI IRQ. */
unsigned char irqs[4] = { PIDE_IRQ, 0, 0, 0 };
pci_assign_irqs(0, 0xc, irqs);
@@ -572,7 +572,7 @@ static void southbridge_init_func1(struct device *dev)
pci_write_config32(dev, SB1_REG_EXT_PIRQ_ROUTE2, ext_int_routing2);
/* Assign in-chip PCI device IRQs. */
- if (SPI1_IRQ || MOTOR_IRQ) {
+ if ((SPI1_IRQ != 0) || (MOTOR_IRQ != 0)) {
unsigned char irqs[4] = { MOTOR_IRQ, SPI1_IRQ, 0, 0 };
pci_assign_irqs(0, 0x10, irqs);
}