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| author | Aamir Bohra <aamir.bohra@intel.com> | 2019-09-30 08:26:00 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-09-30 12:01:08 +0000 |
| commit | ff5eb86aeb3e2129882120150132ba83dd1efea0 (patch) | |
| tree | e416267a46eb946df0eda5a31fa92fda98a7c404 /src/southbridge | |
| parent | 0e1245e3d065287b3f731e92fa45811225462532 (diff) | |
| download | coreboot-ff5eb86aeb3e2129882120150132ba83dd1efea0.tar.xz | |
mb/google/drallion: Clean up devicetree config
* Disable SATA controller and related configs.
* Disable PCIe root ports 10 and related configs.
-> Board uses integrated CnVi for WLAN
* Disable PCIe root ports 12 and related configs.
-> Board uses WWAN intarfaced over USB
Change-Id: If9d49cef290dcccb114afccc3ac34cd072802ea4
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35723
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge')
0 files changed, 0 insertions, 0 deletions