sb/intel/lynxpoint: Update LPT-H magic as per RC 1.9.1

Add the missing PM initialization for Lynxpoint-H. There are some small
changes to Lynxpoint-LP, since some register writes are common among
both PCH variants. This is based on version 1.9.1 of reference code.

Remove the `pch_fixups()` function. The DMI configuration is specific to
Lynxpoint-H. It is not valid for Lynxpoint-LP, which does not have DMI.

Tested on Asrock B85M Pro4, still boots. Registers have the new values.
Without this patch, nearly all registers don't have the expected values.

Change-Id: Ie3f96f2106f3c23aeb694dd6fb343099fc5784e5
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47208
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

2 files changed, 122 insertions, 15 deletions

diff --git a/src/southbridge/intel/lynxpoint/early_pch.c b/src/southbridge/intel/lynxpoint/early_pch.c
index 75aaf67737..2d0a53d799 100644
--- a/src/southbridge/intel/lynxpoint/early_pch.c
+++ b/src/southbridge/intel/lynxpoint/early_pch.c
@@ -113,6 +113,17 @@ int early_pch_init(void)
 
 	RCBA32_OR(FD, PCH_DISABLE_ALWAYS);
 
+	RCBA32(0x2088) = 0x00109000;
+
+	RCBA32_OR(0x20ac, 1 << 30);
+
+	if (!pch_is_lp()) {
+		RCBA32_AND_OR(0x2340, ~(0xff <<  0), 0x1b <<  0);
+		RCBA32_AND_OR(0x2340, ~(0xff << 16), 0x3a << 16);
+
+		RCBA32(0x2324) = 0x00854c74;
+	}
+
 	wake_from_s3 = southbridge_detect_s3_resume();
 
 	elog_boot_notify(wake_from_s3);
diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c
index a37f1a267b..cf80e64ba4 100644
--- a/src/southbridge/intel/lynxpoint/lpc.c
+++ b/src/southbridge/intel/lynxpoint/lpc.c
@@ -286,10 +286,118 @@ static void pch_power_options(struct device *dev)
 	RCBA16(0x3f02) = reg16;
 }
 
+static void configure_dmi_pm(struct device *dev)
+{
+	struct device *const pcie_dev = pcidev_on_root(0x1c, 0);
+
+	/* Additional PCH DMI programming steps */
+
+	/* EL0 */
+	u32 reg32 = 3 << 12;
+
+	/* EL1 */
+	if (pcie_dev && !(pci_read_config8(pcie_dev, 0xf5) & 1 << 0))
+		reg32 |= 2 << 15;
+	else
+		reg32 |= 4 << 15;
+
+	RCBA32_AND_OR(0x21a4, ~(7 << 15 | 7 << 12), reg32);
+
+	RCBA32_AND_OR(0x2348, ~0xf, 0);
+
+	/* Clear prior to enabling DMI ASPM */
+	RCBA32_AND_OR(0x2304, ~(1 << 10), 0);
+
+	RCBA32_OR(0x21a4, 3 << 10);
+
+	RCBA16(0x21a8) |= 3 << 0;
+
+	/* Set again after enabling DMI ASPM */
+	RCBA32_OR(0x2304, 1 << 10);
+}
+
 /* LynxPoint PCH Power Management init */
 static void lpt_pm_init(struct device *dev)
 {
-	printk(BIOS_DEBUG, "LynxPoint PM init\n");
+	struct southbridge_intel_lynxpoint_config *config = dev->chip_info;
+
+	struct device *const pcie_dev = pcidev_on_root(0x1c, 0);
+
+	printk(BIOS_DEBUG, "LynxPoint H PM init\n");
+
+	/* Configure additional PM */
+	pci_write_config8(dev, 0xa9, 0x46);
+
+	pci_or_config32(dev, PMIR, PMIR_CF9LOCK);
+
+	/* Step 3 is skipped */
+
+	/* Program DMI Hardware Width Control (thermal throttling) */
+	u32 reg32 = 0;
+	reg32 |= 1 <<  0;	/* DMI Thermal Sensor Autonomous Width Enable */
+	reg32 |= 0 <<  4;	/* Thermal Sensor 0 Target Width */
+	reg32 |= 1 <<  6;	/* Thermal Sensor 1 Target Width */
+	reg32 |= 1 <<  8;	/* Thermal Sensor 2 Target Width */
+	reg32 |= 2 << 10;	/* Thermal Sensor 3 Target Width */
+	RCBA32(0x2238) = reg32;
+
+	RCBA32_OR(0x232c, 1 << 0);
+	RCBA32_OR(0x1100, 3 << 13);	/* Assume trunk clock gating is to be enabled */
+
+	RCBA32(0x2304) = 0xc07b8400;	/* DMI misc control */
+
+	RCBA32_OR(0x2314, 1 << 23 | 1 << 5);
+
+	if (pcie_dev)
+		pci_update_config8(pcie_dev, 0xf5, ~0xf, 0x5);
+
+	RCBA32_OR(0x2320, 1 << 1);
+
+	RCBA32(0x3314) = 0x000007bf;
+
+	/* NOTE: Preserve bit 5 */
+	RCBA32_OR(0x3318, 0x0dcf0000);
+
+	RCBA32(0x3324) = 0x04000000;
+	RCBA32(0x3340) = 0x020ddbff;
+
+	RCBA32_OR(0x3344, 1 << 0);
+
+	RCBA32(0x3368) = 0x00041000;
+	RCBA32(0x3378) = 0x3f8ddbff;
+	RCBA32(0x337c) = 0x000001e1;
+	RCBA32(0x3388) = 0x00001000;
+	RCBA32(0x33a0) = 0x00000800;
+	RCBA32(0x33ac) = 0x00001000;
+	RCBA32(0x33b0) = 0x00001000;
+	RCBA32(0x33c0) = 0x00011900;
+	RCBA32(0x33d0) = 0x06000802;
+	RCBA32(0x3a28) = 0x01010000;
+	RCBA32(0x3a2c) = 0x01010404;
+
+	RCBA32_OR(0x33a4, 1 << 0);
+
+	/* DMI power optimizer */
+	RCBA32_OR(0x33d4, 1 << 27);
+	RCBA32_OR(0x33c8, 1 << 27);
+	RCBA32(0x2b14) = 0x1e0a0317;
+	RCBA32(0x2b24) = 0x4000000b;
+	RCBA32(0x2b28) = 0x00000002;
+	RCBA32(0x2b2c) = 0x00008813;
+
+	RCBA32(0x3a80) = 0x01040000;
+	reg32 = 0x01041001;
+	/* Port 1 and 0 disabled */
+	if (config && (config->sata_port_map & ((1 << 1) | (1 << 0))) == 0)
+		reg32 |= (1 << 20) | (1 << 18);
+	/* Port 3 and 2 disabled */
+	if (config && (config->sata_port_map & ((1 << 3) | (1 << 2))) == 0)
+		reg32 |= (1 << 24) | (1 << 26);
+	RCBA32(0x3a84) = reg32;
+	RCBA32(0x3a88) = 0x00000001;
+	RCBA32(0x33d4) = 0xc80bc000;
+
+	configure_dmi_pm(dev);
 }
 
 /* LynxPoint LP PCH Power Management init */
@@ -475,19 +583,6 @@ static void pch_set_acpi_mode(void)
 		apm_control(APM_CNT_ACPI_DISABLE);
 }
 
-static void pch_fixups(struct device *dev)
-{
-	/* Indicate DRAM init done for MRC S3 to know it can resume */
-	pci_or_config8(dev, GEN_PMCON_2, 1 << 7);
-
-	/*
-	 * Enable DMI ASPM in the PCH
-	 */
-	RCBA32_AND_OR(0x2304, ~(1 << 10), 0);
-	RCBA32_OR(0x21a4, (1 << 11) | (1 << 10));
-	RCBA32_OR(0x21a8, 0x3);
-}
-
 static void lpc_init(struct device *dev)
 {
 	printk(BIOS_DEBUG, "pch: %s\n", __func__);
@@ -528,7 +623,8 @@ static void lpc_init(struct device *dev)
 
 	pch_set_acpi_mode();
 
-	pch_fixups(dev);
+	/* Indicate DRAM init done for MRC S3 to know it can resume */
+	pci_or_config8(dev, GEN_PMCON_2, 1 << 7);
 }
 
 static void pch_lpc_add_mmio_resources(struct device *dev)