src: Remove redundant use of ACPI offset(0)

IASL version 20180927 and greater, detects Unnecessary/redundant uses of
the Offset() operator within a Field Unit list.
It then sends a remark "^ Unnecessary/redundant use of Offset"

example:
    OperationRegion (OPR1, SystemMemory, 0x100, 0x100)
    Field (OPR1)
    {
        Offset (0),     // Never needed
        FLD1, 32,
        Offset (4),     // Redundant, offset is already 4 (bytes)
        FLD2, 8,
        Offset (64),    // OK use of Offset.
        FLD3, 16,
    }

We will have those remarks:
dsdt.asl     14:         Offset (0),
Remark   2158 -                 ^ Unnecessary/redundant use of Offset operator

dsdt.asl     16:         Offset (4),
Remark   2158 -                 ^ Unnecessary/redundant use of Offset operator

Change-Id: I260a79ef77025b4befbccc21f5999f89d90c1154
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43283
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

9 files changed, 4 insertions, 12 deletions

diff --git a/src/southbridge/amd/cimx/sb800/acpi/fch.asl b/src/southbridge/amd/cimx/sb800/acpi/fch.asl
index 0c0150de95..0986b69070 100644
--- a/src/southbridge/amd/cimx/sb800/acpi/fch.asl
+++ b/src/southbridge/amd/cimx/sb800/acpi/fch.asl
@@ -213,8 +213,7 @@ Scope(\){
 		PIOD, 0x00000008,
 	}
 	IndexField (PIOI, PIOD, ByteAcc, NoLock, Preserve) {
-		Offset(0x00),	/* MiscControl */
-		, 1,
+		    , 1,	/* MiscControl */
 		T1EE, 1,
 		T2EE, 1,
 		Offset(0x01),	/* MiscStatus */
diff --git a/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl b/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl
index f9944720a8..46096cc66b 100644
--- a/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl
+++ b/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl
@@ -15,7 +15,6 @@ OperationRegion (GNVS, SystemMemory, NVSA, 0xf00)
 Field (GNVS, ByteAcc, NoLock, Preserve)
 {
 	/* Miscellaneous */
-	Offset (0x00),
 	OSYS,	16,	// 0x00 - Operating System
 	SMIF,	 8,	// 0x02 - SMI function
 	PRM0,	 8,	// 0x03 - SMI function parameter
diff --git a/src/southbridge/intel/bd82x6x/acpi/pch.asl b/src/southbridge/intel/bd82x6x/acpi/pch.asl
index 4f08a64e8a..4a033abfb1 100644
--- a/src/southbridge/intel/bd82x6x/acpi/pch.asl
+++ b/src/southbridge/intel/bd82x6x/acpi/pch.asl
@@ -63,8 +63,7 @@ Scope(\)
 	OperationRegion(GPIO, SystemIO, DEFAULT_GPIOBASE, 0x6c)
 	Field(GPIO, ByteAcc, NoLock, Preserve)
 	{
-		Offset(0x00),	// GPIO Use Select
-		GU00, 8,
+		GU00, 8,	// GPIO Use Select
 		GU01, 8,
 		GU02, 8,
 		GU03, 8,
diff --git a/src/southbridge/intel/i82801ix/acpi/globalnvs.asl b/src/southbridge/intel/i82801ix/acpi/globalnvs.asl
index 0a0f25511b..5c9e26ea27 100644
--- a/src/southbridge/intel/i82801ix/acpi/globalnvs.asl
+++ b/src/southbridge/intel/i82801ix/acpi/globalnvs.asl
@@ -15,7 +15,6 @@ OperationRegion (GNVS, SystemMemory, NVSA, 0x100)
 Field (GNVS, ByteAcc, NoLock, Preserve)
 {
 	/* Miscellaneous */
-	Offset (0x00),
 	OSYS,	16,	// 0x00 - Operating System
 	SMIF,	 8,	// 0x02 - SMI function
 	PRM0,	 8,	// 0x03 - SMI function parameter
diff --git a/src/southbridge/intel/i82801ix/acpi/ich9.asl b/src/southbridge/intel/i82801ix/acpi/ich9.asl
index 25a756e87f..f720505c08 100644
--- a/src/southbridge/intel/i82801ix/acpi/ich9.asl
+++ b/src/southbridge/intel/i82801ix/acpi/ich9.asl
@@ -32,8 +32,7 @@ Scope(\)
 	OperationRegion(GPIO, SystemIO, DEFAULT_GPIOBASE, 0x3c)
 	Field(GPIO, ByteAcc, NoLock, Preserve)
 	{
-		Offset(0x00),	// GPIO Use Select
-		GU00, 8,
+		GU00, 8,	// GPIO Use Select
 		GU01, 8,
 		GU02, 8,
 		GU03, 8,
diff --git a/src/southbridge/intel/i82801jx/acpi/globalnvs.asl b/src/southbridge/intel/i82801jx/acpi/globalnvs.asl
index 0a0f25511b..5c9e26ea27 100644
--- a/src/southbridge/intel/i82801jx/acpi/globalnvs.asl
+++ b/src/southbridge/intel/i82801jx/acpi/globalnvs.asl
@@ -15,7 +15,6 @@ OperationRegion (GNVS, SystemMemory, NVSA, 0x100)
 Field (GNVS, ByteAcc, NoLock, Preserve)
 {
 	/* Miscellaneous */
-	Offset (0x00),
 	OSYS,	16,	// 0x00 - Operating System
 	SMIF,	 8,	// 0x02 - SMI function
 	PRM0,	 8,	// 0x03 - SMI function parameter
diff --git a/src/southbridge/intel/i82801jx/acpi/ich10.asl b/src/southbridge/intel/i82801jx/acpi/ich10.asl
index e62f8a1a80..d6136af14f 100644
--- a/src/southbridge/intel/i82801jx/acpi/ich10.asl
+++ b/src/southbridge/intel/i82801jx/acpi/ich10.asl
@@ -33,7 +33,7 @@ Scope(\)
 	OperationRegion(GPIO, SystemIO, DEFAULT_GPIOBASE, 0x3c)
 	Field(GPIO, ByteAcc, NoLock, Preserve)
 	{
-		Offset(0x00),	// GPIO Use Select
+				// GPIO Use Select
 		GU00, 8,
 		GU01, 8,
 		GU02, 8,
diff --git a/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl b/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl
index ccf9b087b3..482718a4ea 100644
--- a/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl
+++ b/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl
@@ -16,7 +16,6 @@ OperationRegion (GNVS, SystemMemory, NVSA, 0xf00)
 Field (GNVS, ByteAcc, NoLock, Preserve)
 {
 	/* Miscellaneous */
-	Offset (0x00),
 	OSYS,	16,	// 0x00 - Operating System
 	SMIF,	 8,	// 0x02 - SMI function
 	PRM0,	 8,	// 0x03 - SMI function parameter
diff --git a/src/southbridge/intel/lynxpoint/acpi/xhci.asl b/src/southbridge/intel/lynxpoint/acpi/xhci.asl
index fbeb56200a..a65b1f6202 100644
--- a/src/southbridge/intel/lynxpoint/acpi/xhci.asl
+++ b/src/southbridge/intel/lynxpoint/acpi/xhci.asl
@@ -12,7 +12,6 @@ Device (XHCI)
 	OperationRegion (XPRT, PCI_Config, 0, 0x100)
 	Field (XPRT, AnyAcc, NoLock, Preserve)
 	{
-		Offset (0x0),
 		DVID, 16,
 		Offset (0x10),
 		, 16,