diff options
| author | Stefan Reinauer <reinauer@chromium.org> | 2012-06-11 14:13:09 -0700 |
|---|---|---|
| committer | Ronald G. Minnich <rminnich@gmail.com> | 2012-07-24 23:16:29 +0200 |
| commit | 49058c0adf348342ea23711f018997816da4056b (patch) | |
| tree | f2c882497733bac60026a7ee083900cbd28af2df /src/southbridge | |
| parent | 999e94cb7a428751cf11be6859dbf29f954bbdc3 (diff) | |
| download | coreboot-49058c0adf348342ea23711f018997816da4056b.tar.xz | |
Fix ME hash functions on Panther Point/Cougar Point
- On Cougar Point there may have been stack corruption during the
ME hash verification
- On Panther Point the ME firmware hash was not passed on to the
OS
Change-Id: I73fc10db63ecff939833fb856a6da1e394155043
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1279
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/southbridge')
| -rw-r--r-- | src/southbridge/intel/bd82x6x/me.c | 2 | ||||
| -rw-r--r-- | src/southbridge/intel/bd82x6x/me_8.x.c | 16 |
2 files changed, 10 insertions, 8 deletions
diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c index a1ae06dfd5..1b7b2623c2 100644 --- a/src/southbridge/intel/bd82x6x/me.c +++ b/src/southbridge/intel/bd82x6x/me.c @@ -621,7 +621,7 @@ static int intel_mei_setup(device_t dev) static int intel_me_extend_valid(device_t dev) { struct me_heres status; - u32 extend[] = {0}; + u32 extend[8] = {0}; int i, count = 0; pci_read_dword_ptr(dev, &status, PCI_ME_HERES); diff --git a/src/southbridge/intel/bd82x6x/me_8.x.c b/src/southbridge/intel/bd82x6x/me_8.x.c index 1bb2ce38dc..c7a69fe5c4 100644 --- a/src/southbridge/intel/bd82x6x/me_8.x.c +++ b/src/southbridge/intel/bd82x6x/me_8.x.c @@ -49,6 +49,7 @@ #if CONFIG_CHROMEOS #include <vendorcode/google/chromeos/chromeos.h> +#include <vendorcode/google/chromeos/gnvs.h> #endif #ifndef __SMM__ @@ -622,7 +623,7 @@ static int intel_mei_setup(device_t dev) static int intel_me_extend_valid(device_t dev) { struct me_heres status; - u32 extend; + u32 extend[8] = {0}; int i, count = 0; pci_read_dword_ptr(dev, &status, PCI_ME_HERES); @@ -651,16 +652,17 @@ static int intel_me_extend_valid(device_t dev) return -1; } - /* - * TODO(dlaurie) Verify the hash against a saved good value. - */ - for (i = 0; i < count; ++i) { - extend = pci_read_config32(dev, PCI_ME_HER(i)); - printk(BIOS_DEBUG, "%08x", extend); + extend[i] = pci_read_config32(dev, PCI_ME_HER(i)); + printk(BIOS_DEBUG, "%08x", extend[i]); } printk(BIOS_DEBUG, "\n"); +#if CONFIG_CHROMEOS + /* Save hash in NVS for the OS to verify */ + chromeos_set_me_hash(extend, count); +#endif + return 0; } |