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| author | Angel Pons <th3fanbus@gmail.com> | 2020-07-07 22:10:14 +0200 |
|---|---|---|
| committer | Michael Niewöhner <c0d3z3r0@review.coreboot.org> | 2020-07-09 21:22:17 +0000 |
| commit | 4a1938f186091ea69fb8dcf480477eb5259573da (patch) | |
| tree | 817152b933e37c9a2ffb9058bc413f7fc3d6c7fc /src/southbridge | |
| parent | bab37a2a2dc59a4a0c4b2fcaedccd035baa21404 (diff) | |
| download | coreboot-4a1938f186091ea69fb8dcf480477eb5259573da.tar.xz | |
sb/intel/bd82x6x/pcie.c: Drop dead code
This code is not even being build-tested. Drop it before it grows moss.
Change-Id: Icd6b3226814f48c4cdd2c2f879c66cb6847a14e9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43216
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge')
| -rw-r--r-- | src/southbridge/intel/bd82x6x/pcie.c | 12 |
1 files changed, 0 insertions, 12 deletions
diff --git a/src/southbridge/intel/bd82x6x/pcie.c b/src/southbridge/intel/bd82x6x/pcie.c index c381d33b57..2eff162bd5 100644 --- a/src/southbridge/intel/bd82x6x/pcie.c +++ b/src/southbridge/intel/bd82x6x/pcie.c @@ -219,18 +219,6 @@ static void pci_init(struct device *dev) pci_update_config16(dev, PCI_BRIDGE_CONTROL, ~PCI_BRIDGE_CTL_PARITY, PCI_BRIDGE_CTL_NO_ISA); -#ifdef EVEN_MORE_DEBUG - u32 reg32; - reg32 = pci_read_config32(dev, 0x20); - printk(BIOS_SPEW, " MBL = 0x%08x\n", reg32); - reg32 = pci_read_config32(dev, 0x24); - printk(BIOS_SPEW, " PMBL = 0x%08x\n", reg32); - reg32 = pci_read_config32(dev, 0x28); - printk(BIOS_SPEW, " PMBU32 = 0x%08x\n", reg32); - reg32 = pci_read_config32(dev, 0x2c); - printk(BIOS_SPEW, " PMLU32 = 0x%08x\n", reg32); -#endif - /* Clear errors in status registers. FIXME: Do something? */ reg16 = pci_read_config16(dev, 0x06); //reg16 |= 0xf900; |