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| author | Stefan Reinauer <stepan@openbios.org> | 2005-11-26 00:10:10 +0000 |
|---|---|---|
| committer | Stefan Reinauer <stepan@openbios.org> | 2005-11-26 00:10:10 +0000 |
| commit | 6cc0e084eaf4dbdfa3d2e2295a6b931370c64cb9 (patch) | |
| tree | 8e3e4559a71f9cd4c7f05c6b060f4fbfce574596 /src/southbridge | |
| parent | c49a8120f5bf4545793b3d26d96f9e7b2b6113e9 (diff) | |
| download | coreboot-6cc0e084eaf4dbdfa3d2e2295a6b931370c64cb9.tar.xz | |
first round of agami aruma merge
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2107 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge')
| -rw-r--r-- | src/southbridge/amd/amd8111/amd8111_acpi.c | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/src/southbridge/amd/amd8111/amd8111_acpi.c b/src/southbridge/amd/amd8111/amd8111_acpi.c index f661ab478e..4177041c16 100644 --- a/src/southbridge/amd/amd8111/amd8111_acpi.c +++ b/src/southbridge/amd/amd8111/amd8111_acpi.c @@ -97,6 +97,16 @@ static void acpi_init(struct device *dev) #endif + /* To enable the register 0xcf9 in the IO space + * bit [D5] is set in the amd8111 configuration register. + * The config. reg. is devBx41. Register 0xcf9 allows + * hard reset capability to the system. For the ACPI + * reset.reg values in fadt.c to work this register + * must be enabled. + */ + byte = pci_read_config8(dev, 0x41); + pci_write_config8(dev, 0x41, byte | (1<<6)|(1<<5)); + /* power on after power fail */ on = MAINBOARD_POWER_ON_AFTER_POWER_FAIL; get_option(&on, "power_on_after_fail"); |