summaryrefslogtreecommitdiff
path: root/src/southbridge
diff options
context:
space:
mode:
authorKyösti Mälkki <kyosti.malkki@gmail.com>2019-08-19 13:29:46 +0300
committerKyösti Mälkki <kyosti.malkki@gmail.com>2019-08-20 12:47:25 +0000
commit830e0de40187183c34a1f558d83b65068b649e2a (patch)
treeda85cce0958aaee29d84220386ee63d1c46cf5a4 /src/southbridge
parent9a016236d4d67e0c95245d0e67ab85ba2a242359 (diff)
downloadcoreboot-830e0de40187183c34a1f558d83b65068b649e2a.tar.xz
AGESA,binaryPI: Fix use of chip.h
Change-Id: I123db3a51a8f354359e8ed5040d23111ea4eb8a4 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34996 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Diffstat (limited to 'src/southbridge')
-rw-r--r--src/southbridge/amd/agesa/hudson/hudson.h1
-rw-r--r--src/southbridge/amd/agesa/hudson/sd.c13
-rw-r--r--src/southbridge/amd/pi/hudson/hudson.h1
-rw-r--r--src/southbridge/amd/pi/hudson/sd.c13
4 files changed, 14 insertions, 14 deletions
diff --git a/src/southbridge/amd/agesa/hudson/hudson.h b/src/southbridge/amd/agesa/hudson/hudson.h
index bd49e8f05c..5d9d8494c6 100644
--- a/src/southbridge/amd/agesa/hudson/hudson.h
+++ b/src/southbridge/amd/agesa/hudson/hudson.h
@@ -18,7 +18,6 @@
#define HUDSON_H
#include <device/device.h>
-#include "chip.h"
/* Power management index/data registers */
#define BIOSRAM_INDEX 0xcd4
diff --git a/src/southbridge/amd/agesa/hudson/sd.c b/src/southbridge/amd/agesa/hudson/sd.c
index cc9470e04b..25acf0cc1f 100644
--- a/src/southbridge/amd/agesa/hudson/sd.c
+++ b/src/southbridge/amd/agesa/hudson/sd.c
@@ -18,18 +18,19 @@
#include <device/pci_ids.h>
#include <device/pci_ops.h>
+#include "chip.h"
#include "hudson.h"
static void sd_init(struct device *dev)
{
- u32 stepping;
+ struct southbridge_amd_agesa_hudson_config *sd_chip = dev->chip_info;
+ u32 stepping = pci_read_config32(pcidev_on_root(0x18, 3), 0xFC);
+ u8 sd_mode = 0;
- stepping = pci_read_config32(pcidev_on_root(0x18, 3), 0xFC);
+ if (sd_chip)
+ sd_mode = sd_chip->sd_mode;
- struct southbridge_amd_agesa_hudson_config *sd_chip =
- (struct southbridge_amd_agesa_hudson_config *)(dev->chip_info);
-
- if (sd_chip->sd_mode == 3) { /* SD 3.0 mode */
+ if (sd_mode == 3) { /* SD 3.0 mode */
pci_write_config32(dev, 0xA4, 0x31FEC8B2);
pci_write_config32(dev, 0xA8, 0x00002503);
pci_write_config32(dev, 0xB0, 0x02180C19);
diff --git a/src/southbridge/amd/pi/hudson/hudson.h b/src/southbridge/amd/pi/hudson/hudson.h
index 6afcc651e2..99e372158d 100644
--- a/src/southbridge/amd/pi/hudson/hudson.h
+++ b/src/southbridge/amd/pi/hudson/hudson.h
@@ -19,7 +19,6 @@
#include <types.h>
#include <device/device.h>
-#include "chip.h"
/* Offsets from ACPI_MMIO_BASE
* This is defined by AGESA, but we don't include AGESA headers to avoid
diff --git a/src/southbridge/amd/pi/hudson/sd.c b/src/southbridge/amd/pi/hudson/sd.c
index e4ace38f05..c22b988f53 100644
--- a/src/southbridge/amd/pi/hudson/sd.c
+++ b/src/southbridge/amd/pi/hudson/sd.c
@@ -18,18 +18,19 @@
#include <device/pci_ids.h>
#include <device/pci_ops.h>
+#include "chip.h"
#include "hudson.h"
static void sd_init(struct device *dev)
{
- u32 stepping;
+ struct southbridge_amd_pi_hudson_config *sd_chip = dev->chip_info;
+ u32 stepping = pci_read_config32(pcidev_on_root(0x18, 3), 0xFC);
+ u8 sd_mode = 0;
- stepping = pci_read_config32(pcidev_on_root(0x18, 3), 0xFC);
+ if (sd_chip)
+ sd_mode = sd_chip->sd_mode;
- struct southbridge_amd_pi_hudson_config *sd_chip =
- (struct southbridge_amd_pi_hudson_config *)(dev->chip_info);
-
- if (sd_chip->sd_mode == 3) { /* SD 3.0 mode */
+ if (sd_mode == 3) { /* SD 3.0 mode */
pci_write_config32(dev, 0xA4, 0x31FEC8B2);
pci_write_config32(dev, 0xA8, 0x00002503);
pci_write_config32(dev, 0xB0, 0x02180C19);