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author | Arthur Heymans <arthur@aheymans.xyz> | 2017-04-19 13:19:15 +0200 |
---|---|---|
committer | Martin Roth <martinroth@google.com> | 2017-04-28 17:19:37 +0200 |
commit | 8621a135d40c93445684f7b1e9c77d9aee392978 (patch) | |
tree | 0836e7736671506fa07e161774bd2a9d7cc85389 /src/southbridge | |
parent | 3eff00ec76f91f5dc9ddf39e2e6073f6053c94a1 (diff) | |
download | coreboot-8621a135d40c93445684f7b1e9c77d9aee392978.tar.xz |
sb/nvidia/mcp55: Link early_ctrl.c
Change-Id: I3a55c2e8077fdb10768df287f38efcd5e2e64bdf
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19365
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/southbridge')
-rw-r--r-- | src/southbridge/nvidia/mcp55/Makefile.inc | 1 | ||||
-rw-r--r-- | src/southbridge/nvidia/mcp55/early_ctrl.c | 7 |
2 files changed, 8 insertions, 0 deletions
diff --git a/src/southbridge/nvidia/mcp55/Makefile.inc b/src/southbridge/nvidia/mcp55/Makefile.inc index 9b1e133222..7073b6974e 100644 --- a/src/southbridge/nvidia/mcp55/Makefile.inc +++ b/src/southbridge/nvidia/mcp55/Makefile.inc @@ -20,6 +20,7 @@ ramstage-y += reset.c romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += enable_usbdebug.c ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c romstage-y += early_smbus.c +romstage-y += early_ctrl.c ifeq ($(CONFIG_MCP55_USE_AZA),y) ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/hda_verb.c diff --git a/src/southbridge/nvidia/mcp55/early_ctrl.c b/src/southbridge/nvidia/mcp55/early_ctrl.c index dabf7ad1e4..1f80316b8f 100644 --- a/src/southbridge/nvidia/mcp55/early_ctrl.c +++ b/src/southbridge/nvidia/mcp55/early_ctrl.c @@ -15,7 +15,14 @@ * GNU General Public License for more details. */ +#include <arch/io.h> +#include <console/console.h> #include <reset.h> +#if IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AMDK8) +#include <northbridge/amd/amdk8/amdk8.h> +#else /* CONFIG_NORTHBRIDGE_AMD_AMDFAM10 */ +#include <northbridge/amd/amdfam10/amdfam10.h> +#endif #include "mcp55.h" void soft_reset(void) |