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authorAngel Pons <th3fanbus@gmail.com>2020-07-25 14:03:40 +0200
committerAngel Pons <th3fanbus@gmail.com>2020-07-28 08:52:37 +0000
commit9f78127b61632cbb138bdbfa650c2e9965440d3b (patch)
treeb0f146a3725bcd86b83242b9abb465bd27829681 /src/southbridge
parent172bcc835f0d214444398c57a0ca9eddd2941ecf (diff)
downloadcoreboot-9f78127b61632cbb138bdbfa650c2e9965440d3b.tar.xz
lynxpoint: Factor out PIRQ routing from devicetree
All boards disable PIRQs. They aren't used on modern OSes anyway. Change-Id: I1351fd4a3910e8cf2e9afe51dc2e82c7464de403 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43863 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/southbridge')
-rw-r--r--src/southbridge/intel/lynxpoint/chip.h13
-rw-r--r--src/southbridge/intel/lynxpoint/lpc.c30
2 files changed, 16 insertions, 27 deletions
diff --git a/src/southbridge/intel/lynxpoint/chip.h b/src/southbridge/intel/lynxpoint/chip.h
index ed362a2d65..cba7671ecc 100644
--- a/src/southbridge/intel/lynxpoint/chip.h
+++ b/src/southbridge/intel/lynxpoint/chip.h
@@ -7,19 +7,6 @@
struct southbridge_intel_lynxpoint_config {
/**
- * Interrupt Routing configuration
- * If bit7 is 1, the interrupt is disabled.
- */
- uint8_t pirqa_routing;
- uint8_t pirqb_routing;
- uint8_t pirqc_routing;
- uint8_t pirqd_routing;
- uint8_t pirqe_routing;
- uint8_t pirqf_routing;
- uint8_t pirqg_routing;
- uint8_t pirqh_routing;
-
- /**
* GPI Routing configuration for LynxPoint-H
*
* Only the lower two bits have a meaning:
diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c
index 7082a79d31..898d6f0986 100644
--- a/src/southbridge/intel/lynxpoint/lpc.c
+++ b/src/southbridge/intel/lynxpoint/lpc.c
@@ -96,18 +96,18 @@ static void pch_enable_serial_irqs(struct device *dev)
static void pch_pirq_init(struct device *dev)
{
struct device *irq_dev;
- /* Get the chip configuration */
- config_t *config = dev->chip_info;
- pci_write_config8(dev, PIRQA_ROUT, config->pirqa_routing);
- pci_write_config8(dev, PIRQB_ROUT, config->pirqb_routing);
- pci_write_config8(dev, PIRQC_ROUT, config->pirqc_routing);
- pci_write_config8(dev, PIRQD_ROUT, config->pirqd_routing);
+ const uint8_t pirq = 0x80;
+
+ pci_write_config8(dev, PIRQA_ROUT, pirq);
+ pci_write_config8(dev, PIRQB_ROUT, pirq);
+ pci_write_config8(dev, PIRQC_ROUT, pirq);
+ pci_write_config8(dev, PIRQD_ROUT, pirq);
- pci_write_config8(dev, PIRQE_ROUT, config->pirqe_routing);
- pci_write_config8(dev, PIRQF_ROUT, config->pirqf_routing);
- pci_write_config8(dev, PIRQG_ROUT, config->pirqg_routing);
- pci_write_config8(dev, PIRQH_ROUT, config->pirqh_routing);
+ pci_write_config8(dev, PIRQE_ROUT, pirq);
+ pci_write_config8(dev, PIRQF_ROUT, pirq);
+ pci_write_config8(dev, PIRQG_ROUT, pirq);
+ pci_write_config8(dev, PIRQH_ROUT, pirq);
/* Eric Biederman once said we should let the OS do this.
* I am not so sure anymore he was right.
@@ -122,10 +122,12 @@ static void pch_pirq_init(struct device *dev)
int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN);
switch (int_pin) {
- case 1: /* INTA# */ int_line = config->pirqa_routing; break;
- case 2: /* INTB# */ int_line = config->pirqb_routing; break;
- case 3: /* INTC# */ int_line = config->pirqc_routing; break;
- case 4: /* INTD# */ int_line = config->pirqd_routing; break;
+ case 1: /* INTA# */
+ case 2: /* INTB# */
+ case 3: /* INTC# */
+ case 4: /* INTD# */
+ int_line = pirq;
+ break;
}
if (!int_line)