summaryrefslogtreecommitdiff
path: root/src/southbridge
diff options
context:
space:
mode:
authorAngel Pons <th3fanbus@gmail.com>2020-07-07 22:11:51 +0200
committerMichael Niewöhner <c0d3z3r0@review.coreboot.org>2020-07-09 21:21:27 +0000
commitbab37a2a2dc59a4a0c4b2fcaedccd035baa21404 (patch)
tree8f3a49069a7db81934457e96230fcf1647679350 /src/southbridge
parent0a65b738d590bb1ef8b51120681125ca40b1f6a9 (diff)
downloadcoreboot-bab37a2a2dc59a4a0c4b2fcaedccd035baa21404.tar.xz
sb/intel/i82801gx/pcie.c: Drop dead code
This code is not even being build-tested. Drop it before it grows moss. Change-Id: I0296cb4265c5b68ee9e11b140763b7d50d1da7ea Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43218 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge')
-rw-r--r--src/southbridge/intel/i82801gx/pcie.c11
1 files changed, 0 insertions, 11 deletions
diff --git a/src/southbridge/intel/i82801gx/pcie.c b/src/southbridge/intel/i82801gx/pcie.c
index dcad32250d..6c0ca5d8e3 100644
--- a/src/southbridge/intel/i82801gx/pcie.c
+++ b/src/southbridge/intel/i82801gx/pcie.c
@@ -84,17 +84,6 @@ static void pci_init(struct device *dev)
reg16 |= (1 << 6);
pci_write_config16(dev, 0x50, reg16);
-#ifdef EVEN_MORE_DEBUG
- reg32 = pci_read_config32(dev, 0x20);
- printk(BIOS_SPEW, " MBL = 0x%08x\n", reg32);
- reg32 = pci_read_config32(dev, 0x24);
- printk(BIOS_SPEW, " PMBL = 0x%08x\n", reg32);
- reg32 = pci_read_config32(dev, 0x28);
- printk(BIOS_SPEW, " PMBU32 = 0x%08x\n", reg32);
- reg32 = pci_read_config32(dev, 0x2c);
- printk(BIOS_SPEW, " PMLU32 = 0x%08x\n", reg32);
-#endif
-
/* Clear errors in status registers */
reg16 = pci_read_config16(dev, 0x06);
//reg16 |= 0xf900;