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| author | Angel Pons <th3fanbus@gmail.com> | 2021-03-30 10:49:24 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-04-06 07:09:23 +0000 |
| commit | cc36c4c235eb8e36d5a48477fadc6fb08997c1f2 (patch) | |
| tree | 488f8e660760dc1a7d75ddf84f95e0b2a25d19b0 /src/southbridge | |
| parent | 52e61945588bc327844acc4658426861d63ad189 (diff) | |
| download | coreboot-cc36c4c235eb8e36d5a48477fadc6fb08997c1f2.tar.xz | |
sb/intel/*/smihandler.c: Correct BIOS_CNTL access width
The BIOS_CNTL register is 8 bits wide on all affected platforms.
Change-Id: Iaf9267cf27847d54ed50e1f9ae29011d0e99cf8e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51939
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge')
| -rw-r--r-- | src/southbridge/intel/common/smihandler.c | 4 | ||||
| -rw-r--r-- | src/southbridge/intel/lynxpoint/smihandler.c | 4 |
2 files changed, 4 insertions, 4 deletions
diff --git a/src/southbridge/intel/common/smihandler.c b/src/southbridge/intel/common/smihandler.c index 4279eb88d7..733c625f6c 100644 --- a/src/southbridge/intel/common/smihandler.c +++ b/src/southbridge/intel/common/smihandler.c @@ -374,7 +374,7 @@ static void southbridge_smi_tco(void) if (tco_sts & (1 << 8)) { // BIOSWR u8 bios_cntl; - bios_cntl = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0xdc); + bios_cntl = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xdc); if (bios_cntl & 1) { /* BWE is RW, so the SMI was caused by a @@ -388,7 +388,7 @@ static void southbridge_smi_tco(void) * box. */ printk(BIOS_DEBUG, "Switching back to RO\n"); - pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xdc, + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xdc, (bios_cntl & ~1)); } /* No else for now? */ } else if (tco_sts & (1 << 3)) { /* TIMEOUT */ diff --git a/src/southbridge/intel/lynxpoint/smihandler.c b/src/southbridge/intel/lynxpoint/smihandler.c index c2f34ab242..9c7b269c1f 100644 --- a/src/southbridge/intel/lynxpoint/smihandler.c +++ b/src/southbridge/intel/lynxpoint/smihandler.c @@ -348,7 +348,7 @@ static void southbridge_smi_tco(void) // BIOSWR if (tco_sts & (1 << 8)) { - u8 bios_cntl = pci_read_config16(PCH_LPC_DEV, BIOS_CNTL); + u8 bios_cntl = pci_read_config8(PCH_LPC_DEV, BIOS_CNTL); if (bios_cntl & 1) { /* @@ -362,7 +362,7 @@ static void southbridge_smi_tco(void) * box. */ printk(BIOS_DEBUG, "Switching back to RO\n"); - pci_write_config32(PCH_LPC_DEV, BIOS_CNTL, (bios_cntl & ~1)); + pci_write_config8(PCH_LPC_DEV, BIOS_CNTL, (bios_cntl & ~1)); } /* No else for now? */ } else if (tco_sts & (1 << 3)) { /* TIMEOUT */ /* Handle TCO timeout */ |