AMD Rev F support

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2435 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

6 files changed, 61 insertions, 109 deletions

diff --git a/src/southbridge/amd/amd8111/amd8111_early_ctrl.c b/src/southbridge/amd/amd8111/amd8111_early_ctrl.c
index 542864a58c..9d40076bea 100644
--- a/src/southbridge/amd/amd8111/amd8111_early_ctrl.c
+++ b/src/southbridge/amd/amd8111/amd8111_early_ctrl.c
@@ -10,7 +10,7 @@ static unsigned get_sbdn(unsigned bus)
                 PCI_ID(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_PCI),
                 bus);
 
-        return (dev>>11) & 0x1f;
+        return (dev>>15) & 0x1f;
 
 }
 
diff --git a/src/southbridge/amd/amd8111/amd8111_enable_rom.c b/src/southbridge/amd/amd8111/amd8111_enable_rom.c
index 8c4e4da5da..b8cc5b1a84 100644
--- a/src/southbridge/amd/amd8111/amd8111_enable_rom.c
+++ b/src/southbridge/amd/amd8111/amd8111_enable_rom.c
@@ -6,10 +6,10 @@ static void amd8111_enable_rom(void)
 
 	/* Enable 5MB rom access at 0xFFB00000 - 0xFFFFFFFF */
 	/* Locate the amd8111 */
-	dev = pci_locate_device(PCI_ID(0x1022, 0x7468), 0);
+	dev = pci_io_locate_device(PCI_ID(0x1022, 0x7468), 0);
 
 	/* Set the 5MB enable bits */
-	byte = pci_read_config8(dev, 0x43);
+	byte = pci_io_read_config8(dev, 0x43);
 	byte |= 0xC0;
-	pci_write_config8(dev, 0x43, byte);
+	pci_io_write_config8(dev, 0x43, byte);
 }
diff --git a/src/southbridge/amd/amd8111/amd8111_reset.c b/src/southbridge/amd/amd8111/amd8111_reset.c
index 8a5f3a5135..e3c061d457 100644
--- a/src/southbridge/amd/amd8111/amd8111_reset.c
+++ b/src/southbridge/amd/amd8111/amd8111_reset.c
@@ -2,9 +2,9 @@
 #include <device/pci_ids.h>
 
 #define PCI_DEV(BUS, DEV, FN) ( \
-	(((BUS) & 0xFF) << 16) | \
-	(((DEV) & 0x1f) << 11) | \
-	(((FN)  & 0x7) << 8))
+	(((BUS) & 0xFFF) << 20) | \
+	(((DEV) & 0x1F) << 15) | \
+	(((FN)  & 0x7) << 12))
 
 #define PCI_ID(VENDOR_ID, DEVICE_ID) \
 	((((DEVICE_ID) & 0xFFFF) << 16) | ((VENDOR_ID) & 0xFFFF))
@@ -14,7 +14,7 @@ typedef unsigned device_t;
 static void pci_write_config8(device_t dev, unsigned where, unsigned char value)
 {
         unsigned addr;
-        addr = dev | where;
+        addr = (dev>>4) | where;
         outl(0x80000000 | (addr & ~3), 0xCF8);
         outb(value, 0xCFC + (addr & 3));
 }
@@ -22,7 +22,7 @@ static void pci_write_config8(device_t dev, unsigned where, unsigned char value)
 static void pci_write_config32(device_t dev, unsigned where, unsigned value)
 {
 	unsigned addr;
-        addr = dev | where;
+        addr = (dev>>4) | where;
         outl(0x80000000 | (addr & ~3), 0xCF8);
         outl(value, 0xCFC);
 }
@@ -30,7 +30,7 @@ static void pci_write_config32(device_t dev, unsigned where, unsigned value)
 static unsigned pci_read_config32(device_t dev, unsigned where)
 {
 	unsigned addr;
-        addr = dev | where;
+        addr = (dev>>4) | where;
         outl(0x80000000 | (addr & ~3), 0xCF8);
         return inl(0xCFC);
 }
@@ -58,8 +58,8 @@ void hard_reset(void)
 {
 	device_t dev;
 	unsigned bus;
-        unsigned node = 0;
-        unsigned link = get_sblk();
+	unsigned node = 0;
+	unsigned link = get_sblk();
 
 	/* Find the device.
 	 * There can only be one 8111 on a hypertransport chain/bus.
diff --git a/src/southbridge/broadcom/bcm5785/bcm5785_early_setup.c b/src/southbridge/broadcom/bcm5785/bcm5785_early_setup.c
index ab94327481..8167691dea 100644
--- a/src/southbridge/broadcom/bcm5785/bcm5785_early_setup.c
+++ b/src/southbridge/broadcom/bcm5785/bcm5785_early_setup.c
@@ -71,6 +71,48 @@ static void bcm5785_enable_wdt_port_cf9(void)
         pci_write_config8(dev, 0x40, (1<<2));
 }
 
+static unsigned get_sbdn(unsigned bus)
+{
+        device_t dev;
+
+        /* Find the device.
+         * There can only be one 8111 on a hypertransport chain/bus.
+         */
+        dev = pci_locate_device_on_bus(
+                PCI_ID(0x1166, 0x0036),
+                bus);
+
+        return (dev>>15) & 0x1f;
+
+}
+
+#define SB_VFSMAF 0
+
+static void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn)
+{
+	//ACPI Decode Enable	
+	outb(0x0e, 0xcd6);
+	outb((1<<3), 0xcd7);
+
+	// set port to 0x2060
+	outb(0x67, 0xcd6);
+	outb(0x60, 0xcd7);
+        outb(0x68, 0xcd6);
+        outb(0x20, 0xcd7);
+
+	outb(0x69, 0xcd6);
+	outb(7, 0xcd7);
+
+	outb(0x64, 0xcd6);
+	outb(9, 0xcd7);
+}
+
+static void ldtstop_sb(void)
+{
+	outb(1, 0x2060);
+}
+
+
 static void hard_reset(void)
 {
         bcm5785_enable_wdt_port_cf9();
diff --git a/src/southbridge/nvidia/ck804/ck804_early_setup.c b/src/southbridge/nvidia/ck804/ck804_early_setup.c
index bd14635541..8e0df326c0 100644
--- a/src/southbridge/nvidia/ck804/ck804_early_setup.c
+++ b/src/southbridge/nvidia/ck804/ck804_early_setup.c
@@ -2,58 +2,13 @@
  * Copyright 2004 Tyan Computer
  *  by yhlu@tyan.com
  */
-static int set_ht_link_buffer_count(uint8_t node, uint8_t linkn, uint8_t linkt, unsigned val)
-{
-        uint32_t dword, dword_old;
-        uint8_t link_type;
-        
-        dword = pci_read_config32(PCI_DEV(0,0x18+node,0), 0x98 + (linkn * 0x20));
-        link_type = dword & 0xff;
-        
-        dword_old = dword = pci_read_config32(PCI_DEV(0,0x18+node,0), 0x90 + (linkn * 0x20) );
-        
-        if ( (link_type & 0x7) == linkt ) { 
-                dword = val; 
-        }       
-        
-        if (dword != dword_old) {
-                pci_write_config32(PCI_DEV(0,0x18+node,0), 0x90 + (linkn * 0x20), dword);
-                return 1;
-        }       
-        
-        return 0;
-}
 static int set_ht_link_ck804(uint8_t ht_c_num)
 {
-        int reset_needed;
-        uint8_t i;
-
-        reset_needed = 0;
-
-        for (i = 0; i < ht_c_num; i++) {
-                uint32_t reg;
-                uint8_t nodeid, linkn;
-                uint8_t busn;
-                unsigned val;
-
-                reg = pci_read_config32(PCI_DEV(0,0x18,1), 0xe0 + i * 4);
-		if((reg & 3) != 3) continue; 
-
-                nodeid = ((reg & 0xf0)>>4); 
-                linkn = ((reg & 0xf00)>>8); 
-                busn = (reg & 0xff0000)>>16; 
-
-                reg = pci_read_config32( PCI_DEV(busn, 1, 0), PCI_VENDOR_ID);
-                if ( (reg & 0xffff) == 0x10de ) {
-                        val = 0x01610169;
-                        reset_needed |= set_ht_link_buffer_count(nodeid, linkn, 0x07,val);
-                } 
-        }
-
-        return reset_needed;
+        unsigned vendorid = 0x10de;
+        unsigned val = 0x01610169;
+        set_ht_link_buffer_counts_chain(ht_c_num, vendorid, val);
 }
 
-
 static void setup_ss_table(unsigned index, unsigned where, unsigned control, const unsigned int *register_values, int max)
 {
         int i;
diff --git a/src/southbridge/nvidia/ck804/ck804_early_setup_car.c b/src/southbridge/nvidia/ck804/ck804_early_setup_car.c
index a144f1227a..206ea0f90a 100644
--- a/src/southbridge/nvidia/ck804/ck804_early_setup_car.c
+++ b/src/southbridge/nvidia/ck804/ck804_early_setup_car.c
@@ -3,59 +3,14 @@
  *  by yhlu@tyan.com
  * 2005.12 yhlu make it for car so it could support more ck804s
  */
-static int set_ht_link_buffer_count(uint8_t node, uint8_t linkn, uint8_t linkt, unsigned val)
-{
-        uint32_t dword, dword_old;
-        uint8_t link_type;
-        
-        /* This works on an Athlon64 because unimplemented links return 0 */
-        dword = pci_read_config32(PCI_DEV(0,0x18+node,0), 0x98 + (linkn * 0x20));
-        link_type = dword & 0xff;
-        
-        dword_old = dword = pci_read_config32(PCI_DEV(0,0x18+node,0), 0x90 + (linkn * 0x20) );
-        
-        if ( (link_type & 0x7) == linkt ) { /* Coherent Link only linkt = 3, ncoherent = 7*/
-                dword = val; 
-        }       
-        
-        if (dword != dword_old) {
-                pci_write_config32(PCI_DEV(0,0x18+node,0), 0x90 + (linkn * 0x20), dword);
-                return 1;
-        }       
-        
-        return 0;
-}
+
 static int set_ht_link_ck804(uint8_t ht_c_num)
 {
-        int reset_needed;
-        uint8_t i;
-
-        reset_needed = 0;
-
-        for (i = 0; i < ht_c_num; i++) {
-                uint32_t reg;
-                uint8_t nodeid, linkn;
-                uint8_t busn;
-                unsigned val;
-
-                reg = pci_read_config32(PCI_DEV(0,0x18,1), 0xe0 + i * 4);
-		if((reg & 3) != 3) continue; 
-
-                nodeid = ((reg & 0xf0)>>4);
-                linkn = ((reg & 0xf00)>>8); 
-                busn = (reg & 0xff0000)>>16; 
-
-                reg = pci_read_config32( PCI_DEV(busn, 1, 0), PCI_VENDOR_ID);
-                if ( (reg & 0xffff) == 0x10de ) {
-                        val = 0x01610169;
-                        reset_needed |= set_ht_link_buffer_count(nodeid, linkn, 0x07,val);
-                } 
-        }
-
-        return reset_needed;
+        unsigned vendorid = 0x10de;
+        unsigned val = 0x01610169;
+        set_ht_link_buffer_counts_chain(ht_c_num, vendorid, val);
 }
 
-
 static void setup_ss_table(unsigned index, unsigned where, unsigned control, const unsigned int *register_values, int max)
 {
         int i;