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authorJosef Kellermann <seppk@arcor.de>2011-03-17 12:34:15 +0000
committerPatrick Georgi <patrick.georgi@coresystems.de>2011-03-17 12:34:15 +0000
commitea1c0a714d3916aafd053e22b76ca90dfbdad199 (patch)
tree1a065bdee8e64f0830345ebbfab6be6eb4d3f291 /src/southbridge
parent3eb5e4e9a363b090e957bbf4e3b1d170f3c71022 (diff)
downloadcoreboot-ea1c0a714d3916aafd053e22b76ca90dfbdad199.tar.xz
Fix power_on_after_fail handling on AMD SB600
Bit 0 of pm reg#74 have to be set turn on system after power resumes. See '42661_sb600_rrg_nda_3.02.pdf' (or '46155_sb600_rrg_pub_3.03.pdf') for details, look for 'PwrFailShadow'. [Patrick: I didn't include the get_options reorganization as get_option doesn't overwrite "on" if power_on_after_fail isn't found in CMOS. Style changes were also left out.] Signed-off-by: Josef Kellermann <seppk@arcor.de> Acked-by: Patrick Georgi <patrick.georgi@secunet.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6451 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge')
-rw-r--r--src/southbridge/amd/sb600/sm.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/southbridge/amd/sb600/sm.c b/src/southbridge/amd/sb600/sm.c
index 1a0d6acdd8..8c1dc9029b 100644
--- a/src/southbridge/amd/sb600/sm.c
+++ b/src/southbridge/amd/sb600/sm.c
@@ -94,7 +94,7 @@ static void sm_init(device_t dev)
byte = pm_ioread(0x74);
byte &= ~0x03;
if (on) {
- byte |= 2;
+ byte |= 1 << 0;
}
byte |= 1 << 2;
pm_iowrite(0x74, byte);