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authorKyösti Mälkki <kyosti.malkki@gmail.com>2013-08-13 09:10:31 +0300
committerKyösti Mälkki <kyosti.malkki@gmail.com>2013-09-06 00:39:04 +0200
commit0306b502804ead6f56ad9dee814d0bc5062870f7 (patch)
tree0d7a84d5b7fbc54e19d7e4cd838415bc34d7e543 /src/southbridge
parent690bf2f333322e764262e60fd24802205280df5e (diff)
downloadcoreboot-0306b502804ead6f56ad9dee814d0bc5062870f7.tar.xz
usbdebug: Fixes for LynxPoint LP
Keep the EHCI BAR unchanged to keep usbdebug working. Change-Id: I7fe0eed24a66cb5058b49ee3fc0350d91089ed7a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3477 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
Diffstat (limited to 'src/southbridge')
-rw-r--r--src/southbridge/intel/lynxpoint/Kconfig4
-rw-r--r--src/southbridge/intel/lynxpoint/early_usb.c12
2 files changed, 12 insertions, 4 deletions
diff --git a/src/southbridge/intel/lynxpoint/Kconfig b/src/southbridge/intel/lynxpoint/Kconfig
index 79aba6cf29..3cf9ffe1e5 100644
--- a/src/southbridge/intel/lynxpoint/Kconfig
+++ b/src/southbridge/intel/lynxpoint/Kconfig
@@ -27,7 +27,7 @@ config SOUTH_BRIDGE_OPTIONS # dummy
select SOUTHBRIDGE_INTEL_COMMON
select IOAPIC
select HAVE_HARD_RESET
- select HAVE_USBDEBUG
+ select HAVE_USBDEBUG_OPTIONS
select USE_WATCHDOG_ON_BOOT
select PCIEXP_ASPM
select PCIEXP_COMMON_CLOCK
@@ -42,7 +42,7 @@ config INTEL_LYNXPOINT_LP
config EHCI_BAR
hex
- default 0xfef00000
+ default 0xe8000000
config EHCI_DEBUG_OFFSET
hex
diff --git a/src/southbridge/intel/lynxpoint/early_usb.c b/src/southbridge/intel/lynxpoint/early_usb.c
index d71467e066..9a1a4cb35e 100644
--- a/src/southbridge/intel/lynxpoint/early_usb.c
+++ b/src/southbridge/intel/lynxpoint/early_usb.c
@@ -24,8 +24,16 @@
#include <device/pci_def.h>
#include "pch.h"
-#define PCH_EHCI1_TEMP_BAR0 0xe8000000
-#define PCH_EHCI2_TEMP_BAR0 0xe8000400
+/* HCD_INDEX==2 selects 0:1a.0 (PCH_EHCI2), any other index
+ * selects 0:1d.0 (PCH_EHCI1) for usbdebug use.
+ */
+#if CONFIG_USBDEBUG_HCD_INDEX != 2
+#define PCH_EHCI1_TEMP_BAR0 CONFIG_EHCI_BAR
+#define PCH_EHCI2_TEMP_BAR0 (PCH_EHCI1_TEMP_BAR0 + 0x400)
+#else
+#define PCH_EHCI2_TEMP_BAR0 CONFIG_EHCI_BAR
+#define PCH_EHCI1_TEMP_BAR0 (PCH_EHCI2_TEMP_BAR0 + 0x400)
+#endif
/*
* Setup USB controller MMIO BAR to prevent the