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authorDuncan Laurie <dlaurie@chromium.org>2013-04-23 13:44:37 -0700
committerAlexandru Gagniuc <mr.nuke.me@gmail.com>2013-11-24 08:45:25 +0100
commit15de7cb4224b6add9a65d083e9a2e8484ae511b8 (patch)
treecf7f2d008c6a5b6fcbd058356f3c681054de7bdc /src/southbridge
parent55ad9724322739a862745a71806af8d9a870601b (diff)
downloadcoreboot-15de7cb4224b6add9a65d083e9a2e8484ae511b8.tar.xz
lynxpoint: Add a function to set an individual GPIO
This will be used in a later commit to do some specific power sequencing. Change-Id: Id7f033bb80aed915c2498ea910cb3ac7290da37f Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/48947 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4137 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Diffstat (limited to 'src/southbridge')
-rw-r--r--src/southbridge/intel/lynxpoint/gpio.c19
-rw-r--r--src/southbridge/intel/lynxpoint/lp_gpio.c14
-rw-r--r--src/southbridge/intel/lynxpoint/pch.h4
3 files changed, 37 insertions, 0 deletions
diff --git a/src/southbridge/intel/lynxpoint/gpio.c b/src/southbridge/intel/lynxpoint/gpio.c
index b492068ccd..147a1c013b 100644
--- a/src/southbridge/intel/lynxpoint/gpio.c
+++ b/src/southbridge/intel/lynxpoint/gpio.c
@@ -109,3 +109,22 @@ unsigned get_gpios(const int *gpio_num_array)
}
return vector;
}
+
+void set_gpio(int gpio_num, int value)
+{
+ static const int gpio_reg_offsets[] = {0xc, 0x38, 0x48};
+ u16 gpio_base = get_gpio_base();
+ int index, bit;
+ u32 config;
+
+ if (gpio_num > MAX_GPIO_NUMBER)
+ return; /* Just ignore wrong gpio numbers. */
+
+ index = gpio_num / 32;
+ bit = gpio_num % 32;
+
+ config = inl(gpio_base + gpio_reg_offsets[index]);
+ config &= ~(1 << bit);
+ config |= value << bit;
+ outl(config, gpio_base + gpio_reg_offsets[index]);
+}
diff --git a/src/southbridge/intel/lynxpoint/lp_gpio.c b/src/southbridge/intel/lynxpoint/lp_gpio.c
index d64555e668..b90e5ba4b8 100644
--- a/src/southbridge/intel/lynxpoint/lp_gpio.c
+++ b/src/southbridge/intel/lynxpoint/lp_gpio.c
@@ -107,3 +107,17 @@ unsigned get_gpios(const int *gpio_num_array)
}
return vector;
}
+
+void set_gpio(int gpio_num, int value)
+{
+ u16 gpio_base = get_gpio_base();
+ u32 conf0;
+
+ if (gpio_num > MAX_GPIO_NUMBER)
+ return;
+
+ conf0 = inl(gpio_base + GPIO_CONFIG0(gpio_num));
+ conf0 &= ~GPO_LEVEL_MASK;
+ conf0 |= value << GPO_LEVEL_SHIFT;
+ outl(conf0, gpio_base + GPIO_CONFIG0(gpio_num));
+}
diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h
index c04957308f..4bdb9268e9 100644
--- a/src/southbridge/intel/lynxpoint/pch.h
+++ b/src/southbridge/intel/lynxpoint/pch.h
@@ -193,6 +193,10 @@ int get_gpio(int gpio_num);
* the array of gpio pin numbers to scan, terminated by -1.
*/
unsigned get_gpios(const int *gpio_num_array);
+/*
+ * set GPIO pin value
+ */
+void set_gpio(int gpio_num, int value);
#endif
#define MAINBOARD_POWER_OFF 0