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authorAaron Durbin <adurbin@chromium.org>2016-08-05 21:23:37 -0500
committerMartin Roth <martinroth@google.com>2016-08-08 18:37:37 +0200
commit16246ea9ce8a5982ec3ad465f1ea12a91abbc39e (patch)
tree3d2447ce12aed51589084049e8aba5ed1fd9894d /src/southbridge
parent968ddf27e2a238be2aa4757700f279366fde0b2b (diff)
downloadcoreboot-16246ea9ce8a5982ec3ad465f1ea12a91abbc39e.tar.xz
chromeos chipsets: select RTC usage
Since RTC is now a Kconfig ensure RTC is selected on the x86 chipsets which are in Chrome OS devices. This allows the eventlog to have proper timestamps instead of all zeros. BUG=chrome-os-partner:55993 Change-Id: I24ae7d9b3bf43a5791d4dc04aae018ce17fda72b Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16086 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/southbridge')
-rw-r--r--src/southbridge/intel/bd82x6x/Kconfig1
-rw-r--r--src/southbridge/intel/lynxpoint/Kconfig1
2 files changed, 2 insertions, 0 deletions
diff --git a/src/southbridge/intel/bd82x6x/Kconfig b/src/southbridge/intel/bd82x6x/Kconfig
index a6009cd81f..6522cce848 100644
--- a/src/southbridge/intel/bd82x6x/Kconfig
+++ b/src/southbridge/intel/bd82x6x/Kconfig
@@ -37,6 +37,7 @@ config SOUTH_BRIDGE_OPTIONS # dummy
select ACPI_SATA_GENERATOR
select HAVE_INTEL_FIRMWARE
select SOUTHBRIDGE_INTEL_COMMON_GPIO
+ select RTC
config EHCI_BAR
hex
diff --git a/src/southbridge/intel/lynxpoint/Kconfig b/src/southbridge/intel/lynxpoint/Kconfig
index 7615e69cc3..31a7db3fa2 100644
--- a/src/southbridge/intel/lynxpoint/Kconfig
+++ b/src/southbridge/intel/lynxpoint/Kconfig
@@ -31,6 +31,7 @@ config SOUTH_BRIDGE_OPTIONS # dummy
select SPI_FLASH
select HAVE_INTEL_FIRMWARE
select HAVE_SPI_CONSOLE_SUPPORT
+ select RTC
select SOUTHBRIDGE_INTEL_COMMON_GPIO if !INTEL_LYNXPOINT_LP
config INTEL_LYNXPOINT_LP