diff options
| author | Duncan Laurie <dlaurie@chromium.org> | 2012-12-19 13:17:06 -0800 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2013-03-18 18:49:07 +0100 |
| commit | 18af4d23f6b17827dda50d17d8dc9da5b2656eef (patch) | |
| tree | 5e6deb5e21f8fa3eed50070feed7dc85f8c492fd /src/southbridge | |
| parent | ad93552b86579afd29e99da1b2fcacb0d872cd1a (diff) | |
| download | coreboot-18af4d23f6b17827dda50d17d8dc9da5b2656eef.tar.xz | |
lynxpoint: Move a bit of generic RCBA into early_pch
Rather than have to repeat this bit in every mainboard.
Also, remove the reset of the RTC power status from here.
We had done this in TOT for current platforms but did not
carry it back to emeraldlake2 where this branched from.
If we clear the status here then we don't get an event
logged later which can be important for the devices that
do not have a CMOS battery.
Change-Id: Ia7131e9d9e7cf86228a285df652a96bcabf05260
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/2683
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/southbridge')
| -rw-r--r-- | src/southbridge/intel/lynxpoint/early_pch.c | 20 |
1 files changed, 13 insertions, 7 deletions
diff --git a/src/southbridge/intel/lynxpoint/early_pch.c b/src/southbridge/intel/lynxpoint/early_pch.c index d0a583fa1b..848eb56262 100644 --- a/src/southbridge/intel/lynxpoint/early_pch.c +++ b/src/southbridge/intel/lynxpoint/early_pch.c @@ -31,6 +31,15 @@ #include "gpio.h" #endif +const struct rcba_config_instruction pch_early_config[] = { + /* Enable IOAPIC */ + RCBA_SET_REG_16(OIC, 0x0100), + /* PCH BWG says to read back the IOAPIC enable register */ + RCBA_READ_REG_16(OIC), + + RCBA_END_CONFIG, +}; + static void pch_enable_bars(void) { /* Setting up Southbridge. In the northbridge code. */ @@ -48,17 +57,10 @@ static void pch_enable_bars(void) static void pch_generic_setup(void) { - u8 reg8; - printk(BIOS_DEBUG, "Disabling Watchdog reboot..."); RCBA32(GCS) = RCBA32(GCS) | (1 << 5); /* No reset */ outw((1 << 11), DEFAULT_PMBASE | 0x60 | 0x08); /* halt timer */ printk(BIOS_DEBUG, " done.\n"); - - // reset rtc power status - reg8 = pci_read_config8(PCH_LPC_DEV, GEN_PMCON_3); - reg8 &= ~(1 << 2); - pci_write_config8(PCH_LPC_DEV, GEN_PMCON_3, reg8); } static int sleep_type_s3(void) @@ -158,6 +160,10 @@ int early_pch_init(const void *gpio_map, /* Enable SMBus for reading SPDs. */ enable_smbus(); + /* Early PCH RCBA settings */ + pch_config_rcba(pch_early_config); + + /* Mainboard RCBA settings */ pch_config_rcba(rcba_config); wake_from_s3 = sleep_type_s3(); |