summaryrefslogtreecommitdiff
path: root/src/southbridge
diff options
context:
space:
mode:
authorAntonello Dettori <dev@dettori.io>2016-09-03 10:45:33 +0200
committerMartin Roth <martinroth@google.com>2016-09-13 17:19:49 +0200
commit1a9da7acf697929392d044f49bad55df25e05ef6 (patch)
treec61656972c98c61efb3d21bd7b525b3426075dd0 /src/southbridge
parent8126daf6f36c2c99edd3f39fa003a53f8fa0d63f (diff)
downloadcoreboot-1a9da7acf697929392d044f49bad55df25e05ef6.tar.xz
southbridge/sis/sis966: transition away from device_t
Replace the use of the old device_t definition inside southbridge/sis/sis966. Change-Id: I9e731fedc6f21eaa2685f794ea2172eb4800628b Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/16488 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/southbridge')
-rw-r--r--src/southbridge/sis/sis966/early_ctrl.c2
-rw-r--r--src/southbridge/sis/sis966/early_smbus.c16
-rw-r--r--src/southbridge/sis/sis966/sis966.h2
3 files changed, 12 insertions, 8 deletions
diff --git a/src/southbridge/sis/sis966/early_ctrl.c b/src/southbridge/sis/sis966/early_ctrl.c
index fc311ae767..74ae1fa05a 100644
--- a/src/southbridge/sis/sis966/early_ctrl.c
+++ b/src/southbridge/sis/sis966/early_ctrl.c
@@ -19,7 +19,7 @@
static unsigned get_sbdn(unsigned bus)
{
- device_t dev;
+ pci_devfn_t dev;
/* Find the device. */
dev = pci_locate_device_on_bus(
diff --git a/src/southbridge/sis/sis966/early_smbus.c b/src/southbridge/sis/sis966/early_smbus.c
index 4a2b867855..5cccedaddf 100644
--- a/src/southbridge/sis/sis966/early_smbus.c
+++ b/src/southbridge/sis/sis966/early_smbus.c
@@ -510,10 +510,12 @@ static const uint8_t SiS_SiS1183_init[44][3]={
*/
static void Init_Share_Memory(uint8_t ShareSize)
{
- device_t dev;
+ pci_devfn_t dev;
- dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS761), 0);
- pci_write_config8(dev, 0x4C, (pci_read_config8(dev, 0x4C) & 0x1F) | (ShareSize << 5));
+ dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS,
+ PCI_DEVICE_ID_SIS_SIS761), 0);
+ pci_write_config8(dev, 0x4C, (pci_read_config8(dev, 0x4C) & 0x1F) |
+ (ShareSize << 5));
}
/* In: => Aperture size
@@ -526,7 +528,7 @@ static void Init_Share_Memory(uint8_t ShareSize)
*/
static void Init_Aper_Size(uint8_t AperSize)
{
- device_t dev;
+ pci_devfn_t dev;
uint16_t SiSAperSizeTable[]={0x0F38, 0x0F30, 0x0F20, 0x0F00, 0x0E00};
dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_AMD, 0x1103), 0);
@@ -538,7 +540,7 @@ static void Init_Aper_Size(uint8_t AperSize)
static void sis_init_stage1(void)
{
- device_t dev;
+ pci_devfn_t dev;
uint8_t temp8;
int i;
uint8_t GUI_En;
@@ -600,7 +602,7 @@ static void sis_init_stage1(void)
static void sis_init_stage2(void)
{
- device_t dev;
+ pci_devfn_t dev;
msr_t msr;
int i;
uint8_t temp8;
@@ -711,7 +713,7 @@ static void sis_init_stage2(void)
static void enable_smbus(void)
{
- device_t dev;
+ pci_devfn_t dev;
uint8_t temp8;
printk(BIOS_DEBUG, "enable_smbus -------->\n");
diff --git a/src/southbridge/sis/sis966/sis966.h b/src/southbridge/sis/sis966/sis966.h
index 31af00297f..61bf0eebdd 100644
--- a/src/southbridge/sis/sis966/sis966.h
+++ b/src/southbridge/sis/sis966/sis966.h
@@ -31,6 +31,8 @@
#define DEBUG_USB 0
#define DEBUG_USB2 0
+#ifndef __SIMPLE_DEVICE__
void sis966_enable(device_t dev);
+#endif
#endif /* SIS966_H */