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authorPatrick Rudolph <siro@das-labor.org>2017-04-12 16:55:32 +0200
committerMartin Roth <martinroth@google.com>2017-05-01 16:23:28 +0200
commit281ccca373c3b7c96452f35815fcf11274678117 (patch)
treef4467013814649bdaf7a0f83c0d9137665d841ee /src/southbridge
parent2be2840a1da29ed50b6eba6c2b7ba68579782a91 (diff)
downloadcoreboot-281ccca373c3b7c96452f35815fcf11274678117.tar.xz
nb/intel/sandybridge/gma: Set up OpRegion in nb code
Set up IGD OpRegion in northbridge and fill in GNVS' aslb. At this point GNVS already has been set up by SSDT injection. Required for future VBT patches that will: * Use ACPI memory instead of CBMEM * Use common implementation to locate VBT * Fill in platform specific values Change-Id: I97c3402ac055991350732e55b0dda042b426c080 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/19310 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/southbridge')
-rw-r--r--src/southbridge/intel/bd82x6x/lpc.c6
1 files changed, 0 insertions, 6 deletions
diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c
index 623482e679..c9fee89062 100644
--- a/src/southbridge/intel/bd82x6x/lpc.c
+++ b/src/southbridge/intel/bd82x6x/lpc.c
@@ -654,10 +654,6 @@ static void set_subsystem(device_t dev, unsigned vendor, unsigned device)
static void southbridge_inject_dsdt(device_t dev)
{
global_nvs_t *gnvs = cbmem_add (CBMEM_ID_ACPI_GNVS, sizeof(*gnvs));
- void *opregion;
-
- /* Calling northbridge code as gnvs contains opregion address. */
- opregion = igd_make_opregion();
if (gnvs) {
const struct i915_gpu_controller_info *gfx = intel_gma_get_controller_info();
@@ -676,8 +672,6 @@ static void southbridge_inject_dsdt(device_t dev)
chromeos_init_vboot(&(gnvs->chromeos));
#endif
- /* IGD OpRegion Base Address */
- gnvs->aslb = (u32)opregion;
/* And tell SMI about it */
smm_setup_structures(gnvs, NULL, NULL);