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authorDuncan Laurie <dlaurie@chromium.org>2013-08-12 13:51:22 -0700
committerPatrick Georgi <patrick@georgi-clan.de>2013-12-21 12:02:50 +0100
commit3106d0ffce85fe07feefb5c488802aab8e9b42f6 (patch)
tree7e99d9f46e99991bd7571500aa89460ecc2e690f /src/southbridge
parent4fb3a61fc6e11686a95c09f63e194fba0cb899f6 (diff)
downloadcoreboot-3106d0ffce85fe07feefb5c488802aab8e9b42f6.tar.xz
haswell: Misc updates from 1.6.1 ref code
These programming sequences were changed in the latest code. Change-Id: Ia4b763a49542635713d11a9ee81f7e7f200bf841 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/65612 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4466 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Diffstat (limited to 'src/southbridge')
-rw-r--r--src/southbridge/intel/lynxpoint/pcie.c3
1 files changed, 0 insertions, 3 deletions
diff --git a/src/southbridge/intel/lynxpoint/pcie.c b/src/southbridge/intel/lynxpoint/pcie.c
index 6a4d75cac2..581b79d1a4 100644
--- a/src/southbridge/intel/lynxpoint/pcie.c
+++ b/src/southbridge/intel/lynxpoint/pcie.c
@@ -649,9 +649,6 @@ static void pch_pcie_early(struct device *dev)
pcie_update_cfg(dev, 0x33c, ~0x00ffffff, 0x854c74);
- /* Set undocumented bits in MPC2 register. */
- pcie_update_cfg(dev, 0xd4, ~0, (1 << 12) | (1 << 6));
-
/* Set Invalid Recieve Range Check Enable in MPC register. */
pcie_update_cfg(dev, 0xd8, ~0, (1 << 25));