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authorElyes HAOUAS <ehaouas@noos.fr>2019-01-21 14:54:31 +0100
committerPatrick Georgi <pgeorgi@google.com>2019-05-10 15:13:33 +0000
commit32b9a99e1670c638cf6e2db2a6274c3f0ab27c85 (patch)
treea03ebeb7912731bc93ebfa9ce852da3bfcc98c03 /src/southbridge
parent8ed01a0e314990539c956b880560526f7c68177d (diff)
downloadcoreboot-32b9a99e1670c638cf6e2db2a6274c3f0ab27c85.tar.xz
nb/intel/i945: Use macro instead of magic number
Change-Id: I028013bd7511b5b9fc80e5f744fcad584cb25fd3 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31027 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge')
-rw-r--r--src/southbridge/intel/i82801gx/i82801gx.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h
index b693b75ccf..a91ffc500b 100644
--- a/src/southbridge/intel/i82801gx/i82801gx.h
+++ b/src/southbridge/intel/i82801gx/i82801gx.h
@@ -94,6 +94,7 @@ int smbus_block_write(unsigned int device, unsigned int cmd, u8 bytes,
#define BIOS_CNTL 0xDC
#define GPIO_BASE 0x48 /* LPC GPIO Base Address Register */
#define GPIO_CNTL 0x4C /* LPC GPIO Control Register */
+#define GPIO_EN (1 << 4)
#define PIRQA_ROUT 0x60
#define PIRQB_ROUT 0x61