Fix some of Peter's suggestions for the Nokia IP530.

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5621 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

12 files changed, 167 insertions, 0 deletions

diff --git a/src/southbridge/Kconfig b/src/southbridge/Kconfig
index 77fe385f57..b0da86ad2b 100644
--- a/src/southbridge/Kconfig
+++ b/src/southbridge/Kconfig
@@ -1,5 +1,6 @@
 source src/southbridge/amd/Kconfig
 source src/southbridge/broadcom/Kconfig
+source src/southbridge/dec/Kconfig
 source src/southbridge/intel/Kconfig
 source src/southbridge/nvidia/Kconfig
 source src/southbridge/ricoh/Kconfig
diff --git a/src/southbridge/Makefile.inc b/src/southbridge/Makefile.inc
index b7e04dbb1f..c78f0ba84a 100644
--- a/src/southbridge/Makefile.inc
+++ b/src/southbridge/Makefile.inc
@@ -1,5 +1,6 @@
 subdirs-y += amd
 subdirs-y += broadcom
+subdirs-y += dec
 subdirs-y += intel
 subdirs-y += nvidia
 subdirs-y += ricoh
diff --git a/src/southbridge/dec/21143/21143.c b/src/southbridge/dec/21143/21143.c
new file mode 100644
index 0000000000..62567c8038
--- /dev/null
+++ b/src/southbridge/dec/21143/21143.c
@@ -0,0 +1,70 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Marc Bertens <mbertens@xs4all.nl>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <device/device.h>
+#include <device/pci_def.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <console/console.h>
+
+/**
+ * The following should be set in the mainboard-specific Kconfig file.
+ */
+#if (!defined(CONFIG_DEC21143_CACHE_LINE_SIZE) || \
+     !defined(CONFIG_DEC21143_EXPANSION_ROM_BASE_ADDRESS) || \
+     !defined(CONFIG_DEC21143_COMMAND_AND_STATUS_CONFIGURATION))
+#error "you must supply these values in your mainboard-specific Kconfig file"
+#endif
+
+/* CONFIG_DEC21143_CACHE_LINE_SIZE try 0x00000000 if unsure */
+/* CONFIG_DEC21143_EXPANSION_ROM_BASE_ADDRESS try 0x00000000 if unsure */
+/* CONFIG_DEC21143_COMMAND_AND_STATUS_CONFIGURATION try 0x02800107 or 0x02800007 if unsure */
+
+/**
+ * This driver take the values from Kconfig and load them in the registers
+ */
+static void dec_21143_enable( device_t dev )
+{
+	printk( BIOS_DEBUG, "Init of DECchip 21143 Kconfig style\n");
+	// Command and Status Configuration Register (Offset 0x04)
+	pci_write_config32( dev, 0x04, CONFIG_DEC21143_COMMAND_AND_STATUS_CONFIGURATION );
+	printk( BIOS_DEBUG, "0x04 = %08x (07 01 80 02)\n", pci_read_config32(dev, 0x04) );
+	// Cache Line Size Register (Offset 0x0C)
+	pci_write_config8( dev, 0x0C, CONFIG_DEC21143_CACHE_LINE_SIZE );
+	printk( BIOS_DEBUG, "0x0c = %08x (00 80 00 00)\n", pci_read_config32(dev, 0x0C) );
+	// Expansion ROM Base Address Register (Offset 0x30)
+	pci_write_config32( dev, 0x30, CONFIG_DEC21143_EXPANSION_ROM_BASE_ADDRESS );
+	printk( BIOS_DEBUG, "0x30 = %08x (0x00000000)\n", pci_read_config32(dev, 0x30) );
+	return;
+}
+
+static struct device_operations dec_21143_ops  = {
+        .read_resources   = pci_dev_read_resources,
+        .set_resources    = pci_dev_set_resources,
+        .enable_resources = pci_dev_enable_resources,
+        .init             = dec_21143_enable,
+        .scan_bus         = 0,
+};
+
+static const struct pci_driver dec_21143_driver __pci_driver = {
+        .ops    = &dec_21143_ops,
+        .vendor = PCI_VENDOR_ID_DEC,
+        .device = PCI_DEVICE_ID_DEC_21142,
+};
diff --git a/src/southbridge/dec/21143/Kconfig b/src/southbridge/dec/21143/Kconfig
new file mode 100644
index 0000000000..bd6bc6787f
--- /dev/null
+++ b/src/southbridge/dec/21143/Kconfig
@@ -0,0 +1,2 @@
+config SOUTHBRIDGE_DEC_21143
+	bool
diff --git a/src/southbridge/dec/21143/Makefile.inc b/src/southbridge/dec/21143/Makefile.inc
new file mode 100644
index 0000000000..a0a84837ba
--- /dev/null
+++ b/src/southbridge/dec/21143/Makefile.inc
@@ -0,0 +1,2 @@
+driver-y += 21143.o
+
diff --git a/src/southbridge/dec/Kconfig b/src/southbridge/dec/Kconfig
new file mode 100644
index 0000000000..acca5e54ed
--- /dev/null
+++ b/src/southbridge/dec/Kconfig
@@ -0,0 +1 @@
+source src/southbridge/dec/21143/Kconfig
diff --git a/src/southbridge/dec/Makefile.inc b/src/southbridge/dec/Makefile.inc
new file mode 100644
index 0000000000..1e75f34316
--- /dev/null
+++ b/src/southbridge/dec/Makefile.inc
@@ -0,0 +1 @@
+subdirs-$(CONFIG_SOUTHBRIDGE_DEC_21143) += 21143
diff --git a/src/southbridge/ti/Kconfig b/src/southbridge/ti/Kconfig
index b101d4940a..8c1fd14fd4 100644
--- a/src/southbridge/ti/Kconfig
+++ b/src/southbridge/ti/Kconfig
@@ -19,3 +19,4 @@
 
 source src/southbridge/ti/pci7420/Kconfig
 source src/southbridge/ti/pcixx12/Kconfig
+source src/southbridge/ti/pci1x2x/Kconfig
diff --git a/src/southbridge/ti/Makefile.inc b/src/southbridge/ti/Makefile.inc
index b3d9fbe804..2328a2805e 100644
--- a/src/southbridge/ti/Makefile.inc
+++ b/src/southbridge/ti/Makefile.inc
@@ -19,3 +19,4 @@
 
 subdirs-$(CONFIG_SOUTHBRIDGE_TI_PCI7420) += pci7420
 subdirs-$(CONFIG_SOUTHBRIDGE_TI_PCIXX12) += pcixx12
+subdirs-$(CONFIG_SOUTHBRIDGE_TI_PCI1X2X) += pci1x2x
diff --git a/src/southbridge/ti/pci1x2x/Kconfig b/src/southbridge/ti/pci1x2x/Kconfig
new file mode 100644
index 0000000000..8442cc3b5e
--- /dev/null
+++ b/src/southbridge/ti/pci1x2x/Kconfig
@@ -0,0 +1,2 @@
+config SOUTHBRIDGE_TI_PCI1X2X
+	bool
diff --git a/src/southbridge/ti/pci1x2x/Makefile.inc b/src/southbridge/ti/pci1x2x/Makefile.inc
new file mode 100644
index 0000000000..ac7f09deab
--- /dev/null
+++ b/src/southbridge/ti/pci1x2x/Makefile.inc
@@ -0,0 +1 @@
+driver-$(CONFIG_SOUTHBRIDGE_TI_PCI1X2X) += pci1x2x.o
diff --git a/src/southbridge/ti/pci1x2x/pci1x2x.c b/src/southbridge/ti/pci1x2x/pci1x2x.c
new file mode 100644
index 0000000000..42ec718e97
--- /dev/null
+++ b/src/southbridge/ti/pci1x2x/pci1x2x.c
@@ -0,0 +1,84 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Marc Bertens <mbertens@xs4all.nl>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include <console/console.h>
+
+#if (	!defined( CONFIG_TI_PCMCIA_CARDBUS_CMDR ) || \
+	!defined( CONFIG_TI_PCMCIA_CARDBUS_CLSR ) || \
+	!defined( CONFIG_TI_PCMCIA_CARDBUS_CLTR	) || \
+	!defined( CONFIG_TI_PCMCIA_CARDBUS_BCR ) || \
+	!defined( CONFIG_TI_PCMCIA_CARDBUS_SCR ) || \
+	!defined( CONFIG_TI_PCMCIA_CARDBUS_MRR ) )
+#error "you must supply these values in your mainboard-specific Kconfig file"
+#endif
+
+static void ti_pci1x2y_init(struct device *dev)
+{
+	printk(BIOS_INFO, "Init of Texas Instruments PCI1x2x PCMCIA/CardBus controller\n");
+	// Command register (offset 04)
+	pci_write_config16( dev, 0x04, CONFIG_TI_PCMCIA_CARDBUS_CMDR );
+	// Cache Line Size Register (offset 0x0C)
+	pci_write_config8( dev, 0x0C, CONFIG_TI_PCMCIA_CARDBUS_CLSR );
+	// CardBus latency timer register (offset 1B)
+	pci_write_config8( dev, 0x1B, CONFIG_TI_PCMCIA_CARDBUS_CLTR );
+	// Bridge control register (offset 3E)
+	pci_write_config16( dev, 0x3E, CONFIG_TI_PCMCIA_CARDBUS_BCR );
+	/** Enable change sub-vendor id
+	 * Clear the bit 5 to enable to write to the sub-vendor/device ids at 40 and 42 */
+	pci_write_config32( dev, 0x80, 0x10 );
+	pci_write_config32( dev, 0x40, PCI_VENDOR_ID_NOKIA );
+	// Now write the correct value for SCR
+	// System Control Register (offset 0x80)
+	pci_write_config32( dev, 0x80, CONFIG_TI_PCMCIA_CARDBUS_SCR );
+	// Multifunction routing register
+	pci_write_config32( dev, 0x8C, CONFIG_TI_PCMCIA_CARDBUS_MRR );
+	// Set Device Control Register (0x92) accordingly
+	pci_write_config8( dev, 0x92, pci_read_config8( dev, 0x92 ) | 0x02 );
+	return;
+}
+
+static struct device_operations ti_pci1x2y_ops  = {
+	.read_resources   = NULL, //pci_dev_read_resources,
+	.set_resources    = pci_dev_set_resources,
+	.enable_resources = pci_dev_enable_resources,
+	.init             = ti_pci1x2y_init,
+	.scan_bus         = 0,
+};
+
+static const struct pci_driver ti_pci1225_driver __pci_driver = {
+        .ops    = &ti_pci1x2y_ops,
+        .vendor = PCI_VENDOR_ID_TI,
+        .device = PCI_DEVICE_ID_TI_1225,
+};
+
+static const struct pci_driver ti_pci1420_driver __pci_driver = {
+        .ops    = &ti_pci1x2y_ops,
+        .vendor = PCI_VENDOR_ID_TI,
+        .device = PCI_DEVICE_ID_TI_1420,
+};
+
+static const struct pci_driver ti_pci1520_driver __pci_driver = {
+        .ops    = &ti_pci1x2y_ops,
+        .vendor = PCI_VENDOR_ID_TI,
+        .device = PCI_DEVICE_ID_TI_1420,
+};