diff options
author | Stefan Reinauer <stepan@coresystems.de> | 2010-07-07 21:59:06 +0000 |
---|---|---|
committer | Stefan Reinauer <stepan@openbios.org> | 2010-07-07 21:59:06 +0000 |
commit | 5e33e827083abe332cf404793d33fa2152a95bab (patch) | |
tree | 253a2f387816e3aff23d1d4f598dd460c7015544 /src/southbridge | |
parent | 42da0e6da6edd2dfe7fd752719ec5d2c94d5e055 (diff) | |
download | coreboot-5e33e827083abe332cf404793d33fa2152a95bab.tar.xz |
fix some more warnings
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5658 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge')
-rw-r--r-- | src/southbridge/amd/rs780/rs780_gfx.c | 31 | ||||
-rw-r--r-- | src/southbridge/amd/sb600/sb600_smbus.c | 5 | ||||
-rw-r--r-- | src/southbridge/amd/sb600/sb600_smbus.h | 4 | ||||
-rw-r--r-- | src/southbridge/amd/sb700/sb700.h | 5 | ||||
-rw-r--r-- | src/southbridge/amd/sb700/sb700_early_setup.c | 4 | ||||
-rw-r--r-- | src/southbridge/amd/sb700/sb700_smbus.c | 4 | ||||
-rw-r--r-- | src/southbridge/amd/sb700/sb700_smbus.h | 2 |
7 files changed, 30 insertions, 25 deletions
diff --git a/src/southbridge/amd/rs780/rs780_gfx.c b/src/southbridge/amd/rs780/rs780_gfx.c index 753af0079f..7decabdac3 100644 --- a/src/southbridge/amd/rs780/rs780_gfx.c +++ b/src/southbridge/amd/rs780/rs780_gfx.c @@ -96,33 +96,33 @@ typedef struct _MMIORANGE MMIORANGE MMIO[8], CreativeMMIO[8]; +#define CIM_STATUS u32 +#define CIM_SUCCESS 0x00000000 +#define CIM_ERROR 0x80000000 +#define CIM_UNSUPPORTED 0x80000001 +#define CIM_DISABLEPORT 0x80000002 + +#define MMIO_ATTRIB_NP_ONLY 1 +#define MMIO_ATTRIB_BOTTOM_TO_TOP 1<<1 +#define MMIO_ATTRIB_SKIP_ZERO 1<<2 + +#ifdef DONT_TRUST_RESOURCE_ALLOCATION static MMIORANGE* AllocMMIO(MMIORANGE* pMMIO) { int i; - for (i=0; i<8; i++) - { + for (i=0; i<8; i++) { if (pMMIO[i].Limit == 0) return &pMMIO[i]; } return 0; } + static void FreeMMIO(MMIORANGE* pMMIO) { pMMIO->Base = 0; pMMIO->Limit = 0; } -#define CIM_STATUS u32 -#define CIM_SUCCESS 0x00000000 -#define CIM_ERROR 0x80000000 -#define CIM_UNSUPPORTED 0x80000001 -#define CIM_DISABLEPORT 0x80000002 - -#define MMIO_ATTRIB_NP_ONLY 1 -#define MMIO_ATTRIB_BOTTOM_TO_TOP 1<<1 -#define MMIO_ATTRIB_SKIP_ZERO 1<<2 - -#ifdef DONT_TRUST_RESOURCE_ALLOCATION static u32 SetMMIO(u32 Base, u32 Limit, u8 Attribute, MMIORANGE *pMMIO) { int i; @@ -584,7 +584,6 @@ static void rs780_internal_gfx_enable(device_t dev) { u32 l_dword; int i; - device_t k8_f0 = 0, k8_f2 = 0; device_t nb_dev = dev_find_slot(0, 0); msr_t sysmem; @@ -617,7 +616,7 @@ static void rs780_internal_gfx_enable(device_t dev) /* LPC DMA Deadlock workaround? */ /* GFX_InitCommon*/ - k8_f0 = dev_find_slot(0, PCI_DEVFN(0x18, 0)); + device_t k8_f0 = dev_find_slot(0, PCI_DEVFN(0x18, 0)); l_dword = pci_read_config32(k8_f0, 0x68); l_dword &= ~(3 << 21); l_dword |= (1 << 21); @@ -632,7 +631,7 @@ static void rs780_internal_gfx_enable(device_t dev) #if (CONFIG_GFXUMA == 1) /* GFX_InitUMA. */ /* Copy CPU DDR Controller to NB MC. */ - k8_f2 = dev_find_slot(0, PCI_DEVFN(0x18, 2)); + device_t k8_f2 = dev_find_slot(0, PCI_DEVFN(0x18, 2)); for (i = 0; i < 12; i++) { l_dword = pci_read_config32(k8_f2, 0x40 + i * 4); diff --git a/src/southbridge/amd/sb600/sb600_smbus.c b/src/southbridge/amd/sb600/sb600_smbus.c index 9e14930b09..8174ce8d44 100644 --- a/src/southbridge/amd/sb600/sb600_smbus.c +++ b/src/southbridge/amd/sb600/sb600_smbus.c @@ -60,7 +60,7 @@ static int smbus_wait_until_done(u32 smbus_io_base) return -3; /* timeout */ } -static int do_smbus_recv_byte(u32 smbus_io_base, u32 device) +int do_smbus_recv_byte(u32 smbus_io_base, u32 device) { u8 byte; @@ -87,8 +87,7 @@ static int do_smbus_recv_byte(u32 smbus_io_base, u32 device) return byte; } -static int do_smbus_send_byte(u32 smbus_io_base, u32 device, - u8 val) +int do_smbus_send_byte(u32 smbus_io_base, u32 device, u8 val) { u8 byte; diff --git a/src/southbridge/amd/sb600/sb600_smbus.h b/src/southbridge/amd/sb600/sb600_smbus.h index 0745776144..684d0e62c4 100644 --- a/src/southbridge/amd/sb600/sb600_smbus.h +++ b/src/southbridge/amd/sb600/sb600_smbus.h @@ -20,8 +20,6 @@ #ifndef SB600_SMBUS_H #define SB600_SMBUS_H -//#include <stdint.h> - #define SMBHSTSTAT 0x0 #define SMBSLVSTAT 0x1 #define SMBHSTCTRL 0x2 @@ -58,6 +56,8 @@ #define axindxp_reg(reg, mask, val) \ alink_ax_indx(1, (reg), (mask), (val)) +int do_smbus_recv_byte(u32 smbus_io_base, u32 device); +int do_smbus_send_byte(u32 smbus_io_base, u32 device, u8 val); int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address); int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, u8 val); diff --git a/src/southbridge/amd/sb700/sb700.h b/src/southbridge/amd/sb700/sb700.h index 81a358bcb1..bf7b297518 100644 --- a/src/southbridge/amd/sb700/sb700.h +++ b/src/southbridge/amd/sb700/sb700.h @@ -49,4 +49,9 @@ extern void set_sm_enable_bits(device_t sm_dev, u32 reg_pos, u32 mask, u32 val); void sb700_enable(device_t dev); +#ifdef __PRE_RAM__ +void sb700_lpc_port80(void); +void sb700_pci_port80(void); +#endif + #endif /* SB700_H */ diff --git a/src/southbridge/amd/sb700/sb700_early_setup.c b/src/southbridge/amd/sb700/sb700_early_setup.c index 4315c39545..22f804ac23 100644 --- a/src/southbridge/amd/sb700/sb700_early_setup.c +++ b/src/southbridge/amd/sb700/sb700_early_setup.c @@ -231,7 +231,7 @@ void soft_reset(void) outb(0x06, 0x0cf9); } -static void sb700_pci_port80(void) +void sb700_pci_port80(void) { u8 byte; device_t dev; @@ -276,7 +276,7 @@ static void sb700_pci_port80(void) pci_write_config8(dev, 0x4A, byte); } -static void sb700_lpc_port80(void) +void sb700_lpc_port80(void) { u8 byte; device_t dev; diff --git a/src/southbridge/amd/sb700/sb700_smbus.c b/src/southbridge/amd/sb700/sb700_smbus.c index ec3f94c7bc..65e6912568 100644 --- a/src/southbridge/amd/sb700/sb700_smbus.c +++ b/src/southbridge/amd/sb700/sb700_smbus.c @@ -63,7 +63,7 @@ static int smbus_wait_until_done(u32 smbus_io_base) return -3; /* timeout */ } -static int do_smbus_recv_byte(u32 smbus_io_base, u32 device) +int do_smbus_recv_byte(u32 smbus_io_base, u32 device) { u8 byte; @@ -90,7 +90,7 @@ static int do_smbus_recv_byte(u32 smbus_io_base, u32 device) return byte; } -static int do_smbus_send_byte(u32 smbus_io_base, u32 device, +int do_smbus_send_byte(u32 smbus_io_base, u32 device, u8 val) { u8 byte; diff --git a/src/southbridge/amd/sb700/sb700_smbus.h b/src/southbridge/amd/sb700/sb700_smbus.h index 6acfa99090..c21a1dc0a2 100644 --- a/src/southbridge/amd/sb700/sb700_smbus.h +++ b/src/southbridge/amd/sb700/sb700_smbus.h @@ -56,6 +56,8 @@ #define axindxp_reg(reg, mask, val) \ alink_ax_indx(1, (reg), (mask), (val)) +int do_smbus_recv_byte(u32 smbus_io_base, u32 device); +int do_smbus_send_byte(u32 smbus_io_base, u32 device, u8 val); int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address); int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, u8 val); |