diff options
author | Vladimir Serbinenko <phcoder@gmail.com> | 2014-09-21 14:31:19 +0200 |
---|---|---|
committer | Vladimir Serbinenko <phcoder@gmail.com> | 2014-10-16 13:35:53 +0200 |
commit | 6985d4ee075ff884315d566853be701e238faac6 (patch) | |
tree | 394856f4a05cd2e063edfe6fb69458f5473d027b /src/southbridge | |
parent | 822bc65b0e8cb9c17721b8b776ec7ecf6ac4129e (diff) | |
download | coreboot-6985d4ee075ff884315d566853be701e238faac6.tar.xz |
amdk8: Move to per-device ACPI
Change-Id: I485791015aa7eaabba53813945c216f5725554b1
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/6948
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/southbridge')
-rw-r--r-- | src/southbridge/amd/amd8111/lpc.c | 30 | ||||
-rw-r--r-- | src/southbridge/amd/rs690/ht.c | 18 | ||||
-rw-r--r-- | src/southbridge/amd/sb600/lpc.c | 18 | ||||
-rw-r--r-- | src/southbridge/amd/sb700/lpc.c | 24 | ||||
-rw-r--r-- | src/southbridge/nvidia/ck804/ht.c | 27 | ||||
-rw-r--r-- | src/southbridge/nvidia/ck804/lpc.c | 7 | ||||
-rw-r--r-- | src/southbridge/nvidia/mcp55/ht.c | 9 | ||||
-rw-r--r-- | src/southbridge/nvidia/mcp55/lpc.c | 19 | ||||
-rw-r--r-- | src/southbridge/via/k8t890/traf_ctrl.c | 40 |
9 files changed, 191 insertions, 1 deletions
diff --git a/src/southbridge/amd/amd8111/lpc.c b/src/southbridge/amd/amd8111/lpc.c index e9bd5fc42b..101c8b325b 100644 --- a/src/southbridge/amd/amd8111/lpc.c +++ b/src/southbridge/amd/amd8111/lpc.c @@ -11,7 +11,13 @@ #include <pc80/isa-dma.h> #include <cpu/x86/lapic.h> #include <arch/ioapic.h> +#if IS_ENABLED(CONFIG_GENERATE_ACPI_TABLES) && IS_ENABLED(CONFIG_PER_DEVICE_ACPI_TABLES) +#include <arch/acpi.h> +#include <arch/acpigen.h> +#include <cpu/amd/model_fxx_powernow.h> +#endif #include <stdlib.h> +#include <string.h> #include "amd8111.h" #define NMI_OFF 0 @@ -112,6 +118,26 @@ static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) ((device & 0xffff) << 16) | (vendor & 0xffff)); } +#if IS_ENABLED(CONFIG_GENERATE_ACPI_TABLES) && IS_ENABLED(CONFIG_PER_DEVICE_ACPI_TABLES) + +extern u16 pm_base; + +unsigned long acpi_fill_mcfg(unsigned long current) +{ + /* Just a dummy */ + return current; +} + +static void southbridge_acpi_fill_ssdt_generator(void) { +#if CONFIG_SET_FIDVID + amd_model_fxx_generate_powernow(pm_base + 0x10, 6, 1); + acpigen_write_mainboard_resources("\\_SB.PCI0.MBRS", "_CRS"); +#endif +} + +#endif + + static struct pci_operations lops_pci = { .set_subsystem = lpci_set_subsystem, }; @@ -121,6 +147,10 @@ static struct device_operations lpc_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = lpc_init, +#if IS_ENABLED(CONFIG_GENERATE_ACPI_TABLES) && IS_ENABLED(CONFIG_PER_DEVICE_ACPI_TABLES) + .write_acpi_tables = acpi_write_hpet, + .acpi_fill_ssdt_generator = southbridge_acpi_fill_ssdt_generator, +#endif .scan_bus = scan_static_bus, .enable = amd8111_enable, .ops_pci = &lops_pci, diff --git a/src/southbridge/amd/rs690/ht.c b/src/southbridge/amd/rs690/ht.c index 7353f767fc..33fce0fcb7 100644 --- a/src/southbridge/amd/rs690/ht.c +++ b/src/southbridge/amd/rs690/ht.c @@ -23,6 +23,7 @@ #include <device/pci_ids.h> #include <device/pci_ops.h> #include <lib.h> +#include <arch/acpi.h> #include "rs690.h" static void ht_dev_set_resources(device_t dev) @@ -84,6 +85,23 @@ static void ht_dev_set_resources(device_t dev) pci_dev_set_resources(dev); } +unsigned long acpi_fill_mcfg(unsigned long current) +{ +#if CONFIG_EXT_CONF_SUPPORT + struct resource *res; + resource_t mmconf_base = EXT_CONF_BASE_ADDRESS; // default + + device_t dev = dev_find_slot(0,PCI_DEVFN(0,0)); + // we report mmconf base + res = probe_resource(dev, 0x1C); + if( res ) + mmconf_base = res->base; + + current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current, mmconf_base, 0x0, 0x0, 0x1f); // Fix me: should i reserve 255 busses ? +#endif + return current; +} + static void ht_dev_read_resources(device_t dev) { #if CONFIG_EXT_CONF_SUPPORT diff --git a/src/southbridge/amd/sb600/lpc.c b/src/southbridge/amd/sb600/lpc.c index 7ef49d147e..b86bcfa237 100644 --- a/src/southbridge/amd/sb600/lpc.c +++ b/src/southbridge/amd/sb600/lpc.c @@ -24,9 +24,13 @@ #include <device/pci_ids.h> #include <device/pci_ops.h> #include <pc80/mc146818rtc.h> +#include <arch/acpi.h> +#include <arch/acpigen.h> #include <pc80/isa-dma.h> #include <arch/io.h> #include <arch/ioapic.h> +#include <arch/acpi.h> +#include <cpu/amd/model_fxx_powernow.h> #include "sb600.h" static void lpc_init(device_t dev) @@ -215,6 +219,16 @@ static void sb600_lpc_enable_resources(device_t dev) sb600_lpc_enable_childrens_resources(dev); } +#if IS_ENABLED(CONFIG_GENERATE_ACPI_TABLES) && IS_ENABLED(CONFIG_PER_DEVICE_ACPI_TABLES) + +extern u16 pm_base; + +static void southbridge_acpi_fill_ssdt_generator(void) { + amd_model_fxx_generate_powernow(pm_base + 8, 6, 1); +} + +#endif + static struct pci_operations lops_pci = { .set_subsystem = pci_dev_set_subsystem, }; @@ -223,6 +237,10 @@ static struct device_operations lpc_ops = { .read_resources = sb600_lpc_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = sb600_lpc_enable_resources, +#if IS_ENABLED(CONFIG_GENERATE_ACPI_TABLES) + .write_acpi_tables = acpi_write_hpet, + .acpi_fill_ssdt_generator = southbridge_acpi_fill_ssdt_generator, +#endif .init = lpc_init, .scan_bus = scan_static_bus, /* .enable = sb600_enable, */ diff --git a/src/southbridge/amd/sb700/lpc.c b/src/southbridge/amd/sb700/lpc.c index a175210be6..58a3cf550a 100644 --- a/src/southbridge/amd/sb700/lpc.c +++ b/src/southbridge/amd/sb700/lpc.c @@ -24,12 +24,22 @@ #include <device/pci_ids.h> #include <device/pci_ops.h> #include <pc80/mc146818rtc.h> +#include <arch/acpi.h> +#include <arch/acpigen.h> #include <pc80/isa-dma.h> #include <arch/io.h> #include <arch/ioapic.h> +#include <arch/acpi.h> #include <cbmem.h> +#include <cpu/amd/model_fxx_powernow.h> #include "sb700.h" +unsigned long acpi_fill_mcfg(unsigned long current) +{ + /* Just a dummy */ + return current; +} + static void lpc_init(device_t dev) { u8 byte; @@ -74,7 +84,6 @@ static void lpc_init(device_t dev) is doing the acpi init */ #if CONFIG_HAVE_ACPI_RESUME { - extern u8 acpi_slp_type; u16 tmp = inw(ACPI_PM1_CNT_BLK); acpi_slp_type = ((tmp & (7 << 10)) >> 10); printk(BIOS_DEBUG, "SLP_TYP type was %x\n", acpi_slp_type); @@ -259,6 +268,15 @@ static void sb700_lpc_enable_resources(device_t dev) sb700_lpc_enable_childrens_resources(dev); } +#if IS_ENABLED(CONFIG_GENERATE_ACPI_TABLES) && IS_ENABLED(CONFIG_PER_DEVICE_ACPI_TABLES) + +static void southbridge_acpi_fill_ssdt_generator(void) { + amd_model_fxx_generate_powernow(ACPI_CPU_CONTROL, 6, 1); +} + +#endif + + static struct pci_operations lops_pci = { .set_subsystem = pci_dev_set_subsystem, }; @@ -267,6 +285,10 @@ static struct device_operations lpc_ops = { .read_resources = sb700_lpc_read_resources, .set_resources = sb700_lpc_set_resources, .enable_resources = sb700_lpc_enable_resources, +#if IS_ENABLED(CONFIG_GENERATE_ACPI_TABLES) && IS_ENABLED(CONFIG_PER_DEVICE_ACPI_TABLES) + .write_acpi_tables = acpi_write_hpet, + .acpi_fill_ssdt_generator = southbridge_acpi_fill_ssdt_generator, +#endif .init = lpc_init, .scan_bus = scan_static_bus, .ops_pci = &lops_pci, diff --git a/src/southbridge/nvidia/ck804/ht.c b/src/southbridge/nvidia/ck804/ht.c index a2ba2957be..6ef39e3e27 100644 --- a/src/southbridge/nvidia/ck804/ht.c +++ b/src/southbridge/nvidia/ck804/ht.c @@ -24,6 +24,33 @@ #include <device/pci_ids.h> #include <device/pci_ops.h> #include "ck804.h" +#include <arch/acpi.h> + +#if IS_ENABLED(CONFIG_GENERATE_ACPI_TABLES) + +unsigned long acpi_fill_mcfg(unsigned long current) +{ + device_t dev; + unsigned long mcfg_base; + + dev = dev_find_slot(0x0, PCI_DEVFN(0x0,0)); + if (!dev) + return current; + + mcfg_base = pci_read_config16(dev, 0x90); + if ((mcfg_base & 0x1000) == 0) + return current; + + mcfg_base = (mcfg_base & 0xf) << 28; + + printk(BIOS_INFO, "mcfg_base %lx.\n", mcfg_base); + + current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) + current, mcfg_base, 0x0, 0x0, 0xff); + return current; +} + +#endif static struct device_operations ht_ops = { .read_resources = pci_dev_read_resources, diff --git a/src/southbridge/nvidia/ck804/lpc.c b/src/southbridge/nvidia/ck804/lpc.c index b3a9b00bc0..a935cee8a0 100644 --- a/src/southbridge/nvidia/ck804/lpc.c +++ b/src/southbridge/nvidia/ck804/lpc.c @@ -30,6 +30,7 @@ #include <pc80/isa-dma.h> #include <arch/io.h> #include <arch/ioapic.h> +#include <arch/acpi.h> #include <cpu/x86/lapic.h> #include <stdlib.h> #include <assert.h> @@ -316,6 +317,9 @@ static struct device_operations lpc_ops = { .read_resources = ck804_lpc_read_resources, .set_resources = ck804_lpc_set_resources, .enable_resources = ck804_lpc_enable_resources, +#if IS_ENABLED(CONFIG_GENERATE_ACPI_TABLES) + .write_acpi_tables = acpi_write_hpet, +#endif .init = lpc_init, .scan_bus = scan_static_bus, // .enable = ck804_enable, @@ -345,6 +349,9 @@ static struct device_operations lpc_slave_ops = { .read_resources = ck804_lpc_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, +#if IS_ENABLED(CONFIG_GENERATE_ACPI_TABLES) + .write_acpi_tables = acpi_write_hpet, +#endif .init = lpc_slave_init, // .enable = ck804_enable, .ops_pci = &ck804_pci_ops, diff --git a/src/southbridge/nvidia/mcp55/ht.c b/src/southbridge/nvidia/mcp55/ht.c index 633221c5d6..2daa5bbdfc 100644 --- a/src/southbridge/nvidia/mcp55/ht.c +++ b/src/southbridge/nvidia/mcp55/ht.c @@ -26,8 +26,17 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <device/pci_ops.h> +#include <arch/acpi.h> #include "mcp55.h" +#if IS_ENABLED(CONFIG_GENERATE_ACPI_TABLES) +unsigned long acpi_fill_mcfg(unsigned long current) +{ + /* Not implemented */ + return current; +} +#endif + static struct device_operations ht_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, diff --git a/src/southbridge/nvidia/mcp55/lpc.c b/src/southbridge/nvidia/mcp55/lpc.c index 585232d712..312348c1fa 100644 --- a/src/southbridge/nvidia/mcp55/lpc.c +++ b/src/southbridge/nvidia/mcp55/lpc.c @@ -34,7 +34,13 @@ #include <arch/io.h> #include <arch/ioapic.h> #include <cpu/x86/lapic.h> +#include <arch/acpi.h> #include <stdlib.h> +#if IS_ENABLED(CONFIG_GENERATE_ACPI_TABLES) +#include <arch/acpi.h> +#include <arch/acpigen.h> +#endif +#include <cpu/amd/model_fxx_powernow.h> #include "mcp55.h" #define NMI_OFF 0 @@ -275,10 +281,23 @@ static const struct pci_driver lpc_driver __pci_driver = { .devices = lpc_ids, }; +#if IS_ENABLED(CONFIG_GENERATE_ACPI_TABLES) && IS_ENABLED(CONFIG_PER_DEVICE_ACPI_TABLES) + +static void southbridge_acpi_fill_ssdt_generator(void) +{ + amd_model_fxx_generate_powernow(0, 0, 0); +} + +#endif + static struct device_operations lpc_slave_ops = { .read_resources = mcp55_lpc_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, +#if IS_ENABLED(CONFIG_GENERATE_ACPI_TABLES) && IS_ENABLED(CONFIG_PER_DEVICE_ACPI_TABLES) + .acpi_fill_ssdt_generator = southbridge_acpi_fill_ssdt_generator, + .write_acpi_tables = acpi_write_hpet, +#endif .init = lpc_slave_init, // .enable = mcp55_enable, .ops_pci = &mcp55_pci_ops, diff --git a/src/southbridge/via/k8t890/traf_ctrl.c b/src/southbridge/via/k8t890/traf_ctrl.c index 464cb6ce05..6eb8e9711f 100644 --- a/src/southbridge/via/k8t890/traf_ctrl.c +++ b/src/southbridge/via/k8t890/traf_ctrl.c @@ -21,6 +21,9 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <console/console.h> +#include <arch/acpi.h> +#include <arch/acpigen.h> +#include <cpu/amd/model_fxx_powernow.h> #include "k8t890.h" extern unsigned long log2(unsigned long x); @@ -122,11 +125,24 @@ static void traf_ctrl_enable_k8t890(struct device *dev) pci_write_config8(dev, 0x60, 0x80 | reg); } +#if IS_ENABLED(CONFIG_GENERATE_ACPI_TABLES) + +static void southbridge_acpi_fill_ssdt_generator(void) { + amd_model_fxx_generate_powernow(0, 0, 0); + acpigen_write_mainboard_resources("\\_SB.PCI0.MBRS", "_CRS"); +} + +#endif + static const struct device_operations traf_ctrl_ops_m = { .read_resources = apic_mmconfig_read_resources, .set_resources = mmconfig_set_resources, .enable_resources = pci_dev_enable_resources, .enable = traf_ctrl_enable_k8m890, +#if IS_ENABLED(CONFIG_GENERATE_ACPI_TABLES) + .write_acpi_tables = acpi_write_hpet, + .acpi_fill_ssdt_generator = southbridge_acpi_fill_ssdt_generator, +#endif .ops_pci = 0, }; @@ -135,11 +151,35 @@ static const struct device_operations traf_ctrl_ops_t = { .set_resources = mmconfig_set_resources, .enable_resources = pci_dev_enable_resources, .enable = traf_ctrl_enable_k8t890, +#if IS_ENABLED(CONFIG_GENERATE_ACPI_TABLES) + .write_acpi_tables = acpi_write_hpet, +#endif .ops_pci = 0, }; /* K8X800 chipsets have no APIC; no 800 PCI ids here */ +unsigned long acpi_fill_mcfg(unsigned long current) +{ + device_t dev; + struct resource *res; + + dev = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_K8T890CE_5, 0); + if (!dev) + dev = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_K8T890CF_5, 0); + if (!dev) + dev = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_K8M890CE_5, 0); + if (!dev) + return current; + + res = find_resource(dev, K8T890_MMCONFIG_MBAR); + if (res) { + current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) + current, res->base, 0x0, 0x0, 0xff); + } + return current; +} + static const struct pci_driver northbridge_driver_t __pci_driver = { .ops = &traf_ctrl_ops_t, |