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authorJonathan A. Kollasch <jakllsch@kollasch.net>2013-10-11 15:52:30 -0500
committerJonathan A. Kollasch <jakllsch@kollasch.net>2013-10-14 02:18:48 +0200
commit948dede9c5a3d67295c4b9528fd11e741459c116 (patch)
tree2334cfc0eb4db2140e105776c355ca29a3ed74e7 /src/southbridge
parentb6795255389ffd2320307dc6848919049016dfbd (diff)
downloadcoreboot-948dede9c5a3d67295c4b9528fd11e741459c116.tar.xz
ck804: obtain stored IOAPIC address from allocator instead of register
Change-Id: Ibdd438455a545aa9266b0fd893d5ff27124ab22c Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net> Reviewed-on: http://review.coreboot.org/3961 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/southbridge')
-rw-r--r--src/southbridge/nvidia/ck804/lpc.c7
1 files changed, 5 insertions, 2 deletions
diff --git a/src/southbridge/nvidia/ck804/lpc.c b/src/southbridge/nvidia/ck804/lpc.c
index d132803b84..4b33a3c58f 100644
--- a/src/southbridge/nvidia/ck804/lpc.c
+++ b/src/southbridge/nvidia/ck804/lpc.c
@@ -32,6 +32,7 @@
#include <arch/ioapic.h>
#include <cpu/x86/lapic.h>
#include <stdlib.h>
+#include <assert.h>
#include "ck804.h"
#define CK804_CHIP_REV 2
@@ -54,14 +55,16 @@ static void lpc_common_init(device_t dev)
{
u8 byte;
u32 dword;
+ struct resource *res;
/* I/O APIC initialization. */
byte = pci_read_config8(dev, 0x74);
byte |= (1 << 0); /* Enable APIC. */
pci_write_config8(dev, 0x74, byte);
- dword = pci_read_config32(dev, PCI_BASE_ADDRESS_1); /* 0x14 */
- setup_ioapic(dword, 0); /* Don't rename IOAPIC ID. */
+ res = find_resource(dev, PCI_BASE_ADDRESS_1); /* IOAPIC */
+ ASSERT(res != NULL);
+ setup_ioapic(res->base, 0); /* Don't rename IOAPIC ID. */
#if 1
dword = pci_read_config32(dev, 0xe4);