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| author | Ronald G. Minnich <rminnich@gmail.com> | 2003-09-30 02:16:47 +0000 |
|---|---|---|
| committer | Ronald G. Minnich <rminnich@gmail.com> | 2003-09-30 02:16:47 +0000 |
| commit | 99dcf231f48433a07cbd47ecb0c23301a6b5b34e (patch) | |
| tree | 0ea4045b3c64e80081c15a706c9308a5b94c4ba6 /src/southbridge | |
| parent | 02360d6672bd95b980f83f464dea4c624b8f8aa2 (diff) | |
| download | coreboot-99dcf231f48433a07cbd47ecb0c23301a6b5b34e.tar.xz | |
The epia now works.
Now to fix the ram ...
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1159 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge')
| -rw-r--r-- | src/southbridge/via/vt8231/vt8231.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/src/southbridge/via/vt8231/vt8231.c b/src/southbridge/via/vt8231/vt8231.c index f395b054fb..3e6372c64f 100644 --- a/src/southbridge/via/vt8231/vt8231.c +++ b/src/southbridge/via/vt8231/vt8231.c @@ -362,7 +362,15 @@ southbridge_init(struct chip *chip, enum chip_pass pass) } } +static void enumerate(struct chip *chip) +{ + extern struct device_operations default_pci_ops_bus; + chip_enumerate(chip); + chip->dev->ops = &default_pci_ops_bus; +} + struct chip_control southbridge_via_vt8231_control = { + .enumerate = enumerate, enable: southbridge_init, name: "VIA vt8231" }; |