summaryrefslogtreecommitdiff
path: root/src/southbridge
diff options
context:
space:
mode:
authorTristan Corrick <tristan@corrick.kiwi>2018-10-31 02:20:28 +1300
committerMartin Roth <martinroth@google.com>2018-11-01 20:27:26 +0000
commit9a085745f155096c8e6522814e46940ffd49da0c (patch)
tree3a01ec3e5ac0e43e5d35bfab42426a5e58f0ef66 /src/southbridge
parenteb38fa7e9588222c6fe1e14a6fcea1b62e83a27d (diff)
downloadcoreboot-9a085745f155096c8e6522814e46940ffd49da0c.tar.xz
sb/intel/lynxpoint: Add PCI IDs for more SKUs
The PCI IDs were taken from the Intel Lynx Point datasheet [1]. [1] IntelĀ® 8 Series/C220 Series Chipset Family Platform Controller Hub (PCH) Datasheet, revision 003, document number 328904. Change-Id: Ie4a264e9325d185334c3d7f7d2ed3c394ac33059 Signed-off-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-on: https://review.coreboot.org/29376 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/southbridge')
-rw-r--r--src/southbridge/intel/lynxpoint/lpc.c5
1 files changed, 5 insertions, 0 deletions
diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c
index 5b09fedff4..6483e6dac9 100644
--- a/src/southbridge/intel/lynxpoint/lpc.c
+++ b/src/southbridge/intel/lynxpoint/lpc.c
@@ -856,6 +856,11 @@ static const unsigned short pci_device_ids[] = {
0x8c4c, /* Q85 SKU */
0x8c4e, /* Q87 SKU */
0x8c4f, /* QM87 SKU */
+ 0x8c50, /* B85 SKU */
+ 0x8c52, /* C222 SKU */
+ 0x8c54, /* C224 SKU */
+ 0x8c56, /* C226 SKU */
+ 0x8c5c, /* H81 SKU */
0x9c41, /* LP Full Featured Engineering Sample */
0x9c43, /* LP Premium SKU */
0x9c45, /* LP Mainstream SKU */