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authorElyes HAOUAS <ehaouas@noos.fr>2020-02-20 20:04:29 +0100
committerPatrick Georgi <pgeorgi@google.com>2020-03-23 09:28:55 +0000
commita5b0bc4b34a553aa17d087fce4d371ea138c00a9 (patch)
tree8a199fbfbf6cf6b6e906a56590f1aa1bc28d2c6b /src/southbridge
parente9aef1fe4548da7bf65f11aec48ff3b40e6461fa (diff)
downloadcoreboot-a5b0bc4b34a553aa17d087fce4d371ea138c00a9.tar.xz
src: capitalize 'APIC'
Change-Id: I487fb53bb2b011d214f002fc200ade2f128a4cc6 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39030 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/southbridge')
-rw-r--r--src/southbridge/intel/i82801dx/smi.c2
-rw-r--r--src/southbridge/intel/i82801ix/smi.c2
-rw-r--r--src/southbridge/intel/i82870/82870.h2
-rw-r--r--src/southbridge/intel/i82870/ioapic.c4
-rw-r--r--src/southbridge/intel/lynxpoint/smi.c2
5 files changed, 6 insertions, 6 deletions
diff --git a/src/southbridge/intel/i82801dx/smi.c b/src/southbridge/intel/i82801dx/smi.c
index 0de98aca9a..26dfc60e5b 100644
--- a/src/southbridge/intel/i82801dx/smi.c
+++ b/src/southbridge/intel/i82801dx/smi.c
@@ -305,7 +305,7 @@ static void aseg_smm_relocate(void)
* - Writes to io 0xb2 (APMC)
* - Writes to the Local Apic ICR with Delivery mode SMI.
*
- * Using the local apic is a bit more tricky. According to
+ * Using the local APIC is a bit more tricky. According to
* AMD Family 11 Processor BKDG no destination shorthand must be
* used.
* The whole SMM initialization is quite a bit hardware specific, so
diff --git a/src/southbridge/intel/i82801ix/smi.c b/src/southbridge/intel/i82801ix/smi.c
index 25d3515134..6e7463fcd3 100644
--- a/src/southbridge/intel/i82801ix/smi.c
+++ b/src/southbridge/intel/i82801ix/smi.c
@@ -111,7 +111,7 @@ static void aseg_smm_relocate(void)
* - Writes to io 0xb2 (APMC)
* - Writes to the Local Apic ICR with Delivery mode SMI.
*
- * Using the local apic is a bit more tricky. According to
+ * Using the local APIC is a bit more tricky. According to
* AMD Family 11 Processor BKDG no destination shorthand must be
* used.
* The whole SMM initialization is quite a bit hardware specific, so
diff --git a/src/southbridge/intel/i82870/82870.h b/src/southbridge/intel/i82870/82870.h
index 1fe40b6e6f..ce76db0682 100644
--- a/src/southbridge/intel/i82870/82870.h
+++ b/src/southbridge/intel/i82870/82870.h
@@ -11,7 +11,7 @@
* GNU General Public License for more details.
*/
-/* for io apic 1461 */
+/* for io APIC 1461 */
#define MBAR 0x10
#define ABAR 0x40
diff --git a/src/southbridge/intel/i82870/ioapic.c b/src/southbridge/intel/i82870/ioapic.c
index 4fbf329342..1f4aa501a8 100644
--- a/src/southbridge/intel/i82870/ioapic.c
+++ b/src/southbridge/intel/i82870/ioapic.c
@@ -43,8 +43,8 @@ static void p64h2_ioapic_init(struct device *dev)
uint32_t memoryBase;
int apic_index, apic_id;
- volatile uint32_t *pIndexRegister; /* io apic io memory space command address */
- volatile uint32_t *pWindowRegister; /* io apic io memory space data address */
+ volatile uint32_t *pIndexRegister; /* io APIC io memory space command address */
+ volatile uint32_t *pWindowRegister; /* io APIC io memory space data address */
apic_index = num_p64h2_ioapics;
num_p64h2_ioapics++;
diff --git a/src/southbridge/intel/lynxpoint/smi.c b/src/southbridge/intel/lynxpoint/smi.c
index ed3c6cce7b..6aef493ee1 100644
--- a/src/southbridge/intel/lynxpoint/smi.c
+++ b/src/southbridge/intel/lynxpoint/smi.c
@@ -76,7 +76,7 @@ static void __unused southbridge_trigger_smi(void)
* - Writes to io 0xb2 (APMC)
* - Writes to the Local Apic ICR with Delivery mode SMI.
*
- * Using the local apic is a bit more tricky. According to
+ * Using the local APIC is a bit more tricky. According to
* AMD Family 11 Processor BKDG no destination shorthand must be
* used.
* The whole SMM initialization is quite a bit hardware specific, so