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| author | Arthur Heymans <arthur@aheymans.xyz> | 2019-05-28 13:39:20 +0200 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2019-07-08 14:54:13 +0000 |
| commit | aadd1d0eaf860c6b503f4f10e17ea0abec6a9939 (patch) | |
| tree | 019ddf5b904d86b65186306ee98ef7cdbc7c731d /src/southbridge | |
| parent | b429c5be15dd4263e8ddb599e1e1f15dd95c3bf0 (diff) | |
| download | coreboot-aadd1d0eaf860c6b503f4f10e17ea0abec6a9939.tar.xz | |
sb/intel/ibexpeak: Use common final SPI OPs setup
This also removes the relevant RCBA replays the mainboard dir.
Change-Id: I75dd9d1bcd09d835f205a51c087d52ebb4e166f6
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33038
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Thomas Heijligen <src@posteo.de>
Diffstat (limited to 'src/southbridge')
| -rw-r--r-- | src/southbridge/intel/ibexpeak/lpc.c | 3 | ||||
| -rw-r--r-- | src/southbridge/intel/ibexpeak/pch.h | 41 |
2 files changed, 3 insertions, 41 deletions
diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index e7162b1e04..fa1ca92d78 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -38,6 +38,7 @@ #include "nvs.h" #include <southbridge/intel/common/pciehp.h> #include <southbridge/intel/common/acpi_pirq_gen.h> +#include <southbridge/intel/common/spi.h> #define NMI_OFF 0 @@ -785,6 +786,8 @@ static void southbridge_fill_ssdt(struct device *device) static void lpc_final(struct device *dev) { + spi_finalize_ops(); + /* Call SMM finalize() handlers before resume */ if (CONFIG(HAVE_SMI_HANDLER)) { if (CONFIG(INTEL_CHIPSET_LOCKDOWN) || diff --git a/src/southbridge/intel/ibexpeak/pch.h b/src/southbridge/intel/ibexpeak/pch.h index 04cc21d475..24a7905ed2 100644 --- a/src/southbridge/intel/ibexpeak/pch.h +++ b/src/southbridge/intel/ibexpeak/pch.h @@ -455,47 +455,6 @@ void southbridge_configure_default_intmap(void); #define DMISCI_STS (1 << 9) #define TCO2_STS 0x66 -/* - * SPI Opcode Menu setup for SPIBAR lockdown - * should support most common flash chips. - */ - -#define SPI_OPMENU_0 0x01 /* WRSR: Write Status Register */ -#define SPI_OPTYPE_0 0x01 /* Write, no address */ - -#define SPI_OPMENU_1 0x02 /* BYPR: Byte Program */ -#define SPI_OPTYPE_1 0x03 /* Write, address required */ - -#define SPI_OPMENU_2 0x03 /* READ: Read Data */ -#define SPI_OPTYPE_2 0x02 /* Read, address required */ - -#define SPI_OPMENU_3 0x05 /* RDSR: Read Status Register */ -#define SPI_OPTYPE_3 0x00 /* Read, no address */ - -#define SPI_OPMENU_4 0x20 /* SE20: Sector Erase 0x20 */ -#define SPI_OPTYPE_4 0x03 /* Write, address required */ - -#define SPI_OPMENU_5 0x9f /* RDID: Read ID */ -#define SPI_OPTYPE_5 0x00 /* Read, no address */ - -#define SPI_OPMENU_6 0xd8 /* BED8: Block Erase 0xd8 */ -#define SPI_OPTYPE_6 0x03 /* Write, address required */ - -#define SPI_OPMENU_7 0x0b /* FAST: Fast Read */ -#define SPI_OPTYPE_7 0x02 /* Read, address required */ - -#define SPI_OPMENU_UPPER ((SPI_OPMENU_7 << 24) | (SPI_OPMENU_6 << 16) | \ - (SPI_OPMENU_5 << 8) | SPI_OPMENU_4) -#define SPI_OPMENU_LOWER ((SPI_OPMENU_3 << 24) | (SPI_OPMENU_2 << 16) | \ - (SPI_OPMENU_1 << 8) | SPI_OPMENU_0) - -#define SPI_OPTYPE ((SPI_OPTYPE_7 << 14) | (SPI_OPTYPE_6 << 12) | \ - (SPI_OPTYPE_5 << 10) | (SPI_OPTYPE_4 << 8) | \ - (SPI_OPTYPE_3 << 6) | (SPI_OPTYPE_2 << 4) | \ - (SPI_OPTYPE_1 << 2) | (SPI_OPTYPE_0)) - -#define SPI_OPPREFIX ((0x50 << 8) | 0x06) /* EWSR and WREN */ - #define SPIBAR_HSFS 0x3804 /* SPI hardware sequence status */ #define SPIBAR_HSFS_SCIP (1 << 5) /* SPI Cycle In Progress */ #define SPIBAR_HSFS_AEL (1 << 2) /* SPI Access Error Log */ |