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authorSven Schnelle <svens@stackframe.org>2011-10-27 13:05:40 +0200
committerStefan Reinauer <stefan.reinauer@coreboot.org>2011-10-27 18:27:07 +0200
commitb2f173e168b5a368eab138a22be5524159532c63 (patch)
treeb4c683ae59071a459d5e36e682215423a04a18d3 /src/southbridge
parent5e4e2290b653b068b1ca55205efd3fbfcc1fda34 (diff)
downloadcoreboot-b2f173e168b5a368eab138a22be5524159532c63.tar.xz
i82801gx: Fix port status in AHCI mode
The code used PCI register 0x92 to enable sata ports, which is wrong. The ICH7 documentation states: "This register is only used in systems that do not support AHCI. In AHCI enabled systems, bits[3:0] must always be set (ICH7R only) / bits[2,0] must always be set (Mobile only), and the status of the port is controlled through AHCI memory space." Writing 0x0f to ICH7-M doesn't seem to hurt, so lets write 0x0f for both variants. This patch makes sata_ahci work on my Thinkpad T60 and X60s. Change-Id: If3b3daec2e5fbaa446de00272ebde01cd8d52475 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/340 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/southbridge')
-rw-r--r--src/southbridge/intel/i82801gx/chip.h1
-rw-r--r--src/southbridge/intel/i82801gx/sata.c9
2 files changed, 9 insertions, 1 deletions
diff --git a/src/southbridge/intel/i82801gx/chip.h b/src/southbridge/intel/i82801gx/chip.h
index b775d39ee8..cc17539d7d 100644
--- a/src/southbridge/intel/i82801gx/chip.h
+++ b/src/southbridge/intel/i82801gx/chip.h
@@ -68,6 +68,7 @@ struct southbridge_intel_i82801gx_config {
uint32_t ide_enable_primary;
uint32_t ide_enable_secondary;
uint32_t sata_ahci;
+ uint32_t sata_ports_implemented;
int c4onc3_enable:1;
};
diff --git a/src/southbridge/intel/i82801gx/sata.c b/src/southbridge/intel/i82801gx/sata.c
index c3908489eb..0e7a1a740c 100644
--- a/src/southbridge/intel/i82801gx/sata.c
+++ b/src/southbridge/intel/i82801gx/sata.c
@@ -30,6 +30,8 @@ static void sata_init(struct device *dev)
{
u32 reg32;
u16 reg16;
+ u32 *ahci_bar;
+
/* Get the chip configuration */
config_t *config = dev->chip_info;
@@ -106,9 +108,14 @@ static void sata_init(struct device *dev)
/* Set Sata Controller Mode. */
pci_write_config8(dev, 0x90, 0x40); // 40=AHCI
- /* Port 0 & 1 enable */
+ /* In ACHI mode, bit[3:0] must always be set
+ * (Port status is controlled through AHCI BAR)
+ */
pci_write_config8(dev, 0x92, 0x0f);
+ ahci_bar = (u32 *)(pci_read_config32(dev, 0x27) & ~0x3ff);
+ ahci_bar[3] = config->sata_ports_implemented;
+
/* SATA Initialization register */
pci_write_config32(dev, 0x94, 0x1a000180);
} else {