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authorGreg Watson <jarrah@users.sourceforge.net>2004-04-22 22:31:49 +0000
committerGreg Watson <jarrah@users.sourceforge.net>2004-04-22 22:31:49 +0000
commitb717e48352fe5466a92431f1597b85f902d75673 (patch)
tree8050b71f88482531883e16fea63275f27fa6d45e /src/southbridge
parentd9dfed56e6384e66294f19851b8488412b3bb751 (diff)
downloadcoreboot-b717e48352fe5466a92431f1597b85f902d75673.tar.xz
start of epia-m port
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1524 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge')
-rw-r--r--src/southbridge/via/vt8235/vt8235.c14
-rw-r--r--src/southbridge/via/vt8235/vt8235_early_serial.c53
-rw-r--r--src/southbridge/via/vt8235/vt8235_early_smbus.c35
3 files changed, 58 insertions, 44 deletions
diff --git a/src/southbridge/via/vt8235/vt8235.c b/src/southbridge/via/vt8235/vt8235.c
index 8d5292fad2..ca5ab32ac3 100644
--- a/src/southbridge/via/vt8235/vt8235.c
+++ b/src/southbridge/via/vt8235/vt8235.c
@@ -229,7 +229,7 @@ static void vt8235_init(struct southbridge_via_vt8235_config *conf)
/* IDE controller */
dev1 = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_1, 0);
/* Power management controller */
- devpwr = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235_4, 0);
+ //devpwr = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235_4, 0);
// enable the internal I/O decode
enables = pci_read_config8(dev0, 0x6C);
@@ -315,22 +315,22 @@ static void vt8235_init(struct southbridge_via_vt8235_config *conf)
// Power management setup
//
// Set ACPI base address to IO 0x4000
- pci_write_config32(devpwr, 0x48, 0x4001);
+ //pci_write_config32(devpwr, 0x48, 0x4001);
// Enable ACPI access (and setup like award)
- pci_write_config8(devpwr, 0x41, 0x84);
+ //pci_write_config8(devpwr, 0x41, 0x84);
// Set hardware monitor base address to IO 0x6000
- pci_write_config32(devpwr, 0x70, 0x6001);
+ //pci_write_config32(devpwr, 0x70, 0x6001);
// Enable hardware monitor (and setup like award)
- pci_write_config8(devpwr, 0x74, 0x01);
+ //pci_write_config8(devpwr, 0x74, 0x01);
// set IO base address to 0x5000
- pci_write_config32(devpwr, 0x90, 0x5001);
+ //pci_write_config32(devpwr, 0x90, 0x5001);
// Enable SMBus
- pci_write_config8(devpwr, 0xd2, 0x01);
+ //pci_write_config8(devpwr, 0xd2, 0x01);
//
// IDE setup
diff --git a/src/southbridge/via/vt8235/vt8235_early_serial.c b/src/southbridge/via/vt8235/vt8235_early_serial.c
index 4e59bbf3ec..3191057811 100644
--- a/src/southbridge/via/vt8235/vt8235_early_serial.c
+++ b/src/southbridge/via/vt8235/vt8235_early_serial.c
@@ -8,12 +8,19 @@
#define SIO_BASE 0x3f0
#define SIO_DATA SIO_BASE+1
-static void vt8235_writesuper(uint8_t reg, uint8_t val)
+static void vt8235_writepnpaddr(uint8_t val)
{
- outb(reg, SIO_BASE);
- outb(val, SIO_DATA);
+ outb(val, 0x2e);
+ outb(val, 0xeb);
}
+static void vt8235_writepnpdata(uint8_t val)
+{
+ outb(val, 0x2f);
+ outb(val, 0xeb);
+}
+
+
static void vt8235_writesiobyte(uint16_t reg, uint8_t val)
{
outb(val, reg);
@@ -34,30 +41,28 @@ static void enable_vt8235_serial(void)
unsigned long x;
uint8_t c;
device_t dev;
- outb(6, 0x80);
- dev = pci_locate_device(PCI_ID(0x1106,0x8235), 0);
-
- if (dev == PCI_DEV_INVALID) {
- outb(7, 0x80);
- die("Serial controller not found\r\n");
- }
-
- /* first, you have to enable the superio and superio config.
- put a 6 reg 80
- */
- c = pci_read_config8(dev, 0x50);
- c |= 6;
- pci_write_config8(dev, 0x50, c);
- outb(2, 0x80);
+ // turn on pnp
+ vt8235_writepnpaddr(0x87);
+ vt8235_writepnpaddr(0x87);
// now go ahead and set up com1.
// set address
- vt8235_writesuper(0xf4, 0xfe);
+ vt8235_writepnpaddr(0x7);
+ vt8235_writepnpdata(0x2);
// enable serial out
- vt8235_writesuper(0xf2, 7);
- // That's it for the sio stuff.
- // movl $SUPERIOCONFIG, %eax
- // movb $9, %dl
- // PCI_WRITE_CONFIG_BYTE
+ vt8235_writepnpaddr(0x30);
+ vt8235_writepnpdata(0x1);
+ // serial port 1 base address (FEh)
+ vt8235_writepnpaddr(0x60);
+ vt8235_writepnpdata(0xfe);
+ // serial port 1 IRQ (04h)
+ vt8235_writepnpaddr(0x70);
+ vt8235_writepnpdata(0x4);
+ // serial port 1 control
+ vt8235_writepnpaddr(0xf0);
+ vt8235_writepnpdata(0x2);
+ // turn of pnp
+ vt8235_writepnpaddr(0xaa);
+
// set up reg to set baud rate.
vt8235_writesiobyte(0x3fb, 0x80);
// Set 115 kb
diff --git a/src/southbridge/via/vt8235/vt8235_early_smbus.c b/src/southbridge/via/vt8235/vt8235_early_smbus.c
index 9d03dacd44..79b73df01e 100644
--- a/src/southbridge/via/vt8235/vt8235_early_smbus.c
+++ b/src/southbridge/via/vt8235/vt8235_early_smbus.c
@@ -1,4 +1,4 @@
-#define SMBUS_IO_BASE 0x5000
+#define SMBUS_IO_BASE 0xf00
#define SMBHSTSTAT 0x0
#define SMBSLVSTAT 0x1
@@ -22,12 +22,15 @@
#define SMBUS_TIMEOUT (100*1000*10)
+#define I2C_TRANS_CMD 0x40
+#define CLOCK_SLAVE_ADDRESS 0x69
+
static void enable_smbus(void)
{
device_t dev;
unsigned char c;
/* Power management controller */
- dev = pci_locate_device(PCI_ID(0x1106,0x8235), 0);
+ dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235), 0);
if (dev == PCI_DEV_INVALID) {
die("SMBUS controller not found\r\n");
@@ -37,20 +40,26 @@ static void enable_smbus(void)
pci_write_config32(dev, 0x90, SMBUS_IO_BASE|1);
// Enable SMBus
- c = pci_read_config8(dev, 0xd2);
- c |= 5;
- pci_write_config8(dev, 0xd2, c);
+ pci_write_config8(dev, 0xd2, (0x4 << 1)|1);
/* make it work for I/O ...
*/
- dev = pci_locate_device(PCI_ID(0x1106,0x8235), 0);
- c = pci_read_config8(dev, 4);
- c |= 1;
- pci_write_config8(dev, 4, c);
- print_debug_hex8(c);
- print_debug(" is the comm register\r\n");
-
- print_debug("SMBus controller enabled\r\n");
+ pci_write_config8(dev, 4, 1);
+
+/* The VT1211 serial port needs 48 mhz clock, on power up it is getting
+ only 24 mhz, there is some mysterious device on the smbus that can
+ fix this...this code below does it. */
+ outb(0xff, SMBUS_IO_BASE+SMBHSTSTAT);
+ outb(0x7f, SMBUS_IO_BASE+SMBHSTDAT0);
+ outb(0x83, SMBUS_IO_BASE+SMBHSTCMD);
+ outb(CLOCK_SLAVE_ADDRESS<<1, SMBUS_IO_BASE+SMBXMITADD);
+ outb(8 | I2C_TRANS_CMD, SMBUS_IO_BASE+SMBHSTCTL);
+
+ for (;;) {
+ c = inb(SMBUS_IO_BASE+SMBHSTSTAT);
+ if (c & 1 == 0)
+ break;
+ }
}