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authorStefan Reinauer <reinauer@chromium.org>2015-03-16 16:50:27 -0700
committerStefan Reinauer <stefan.reinauer@coreboot.org>2015-03-17 04:55:52 +0100
commitc3d15a72104b844baab6f99a32c74c09c49335b6 (patch)
tree4f099f52a9118c72d41325508ca18e79dcb5e1ec /src/southbridge
parent45a225b05dbc22c5aff3c8baf927a68142f6be86 (diff)
downloadcoreboot-c3d15a72104b844baab6f99a32c74c09c49335b6.tar.xz
Intel common SPI: Fix compilation breakage from refactoring
When the Intel SPI drivers were refactored, compilation for Chrome OS devices broke, because ELOG uses the SPI driver in SMM. Change-Id: If2b2da5d526196ed742e17409b01a381417d0ce8 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/8701 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
Diffstat (limited to 'src/southbridge')
-rw-r--r--src/southbridge/intel/common/spi.c2
1 files changed, 2 insertions, 0 deletions
diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c
index d6ab01a545..1780fc09ce 100644
--- a/src/southbridge/intel/common/spi.c
+++ b/src/southbridge/intel/common/spi.c
@@ -360,6 +360,7 @@ void spi_init(void)
bios_cntl &= ~(1 << 5);
pci_write_config_byte(dev, 0xdc, bios_cntl | 0x1);
}
+#ifndef __SMM__
static void spi_init_cb(void *unused)
{
spi_init();
@@ -368,6 +369,7 @@ static void spi_init_cb(void *unused)
BOOT_STATE_INIT_ENTRIES(spi_init_bscb) = {
BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, spi_init_cb, NULL),
};
+#endif
int spi_claim_bus(struct spi_slave *slave)
{